Abstract: A light source module includes a substrate unit for mounting multiple light emitting diodes thereon to electrically connecting them; first and second electrical connecting terminals for supplying a current to the light emitting diodes based on a voltage applied from outside the substrate unit; and a characteristic setting unit for presetting characteristic information corresponding to a electrical characteristic of the light emitting diodes. Further, the light source module includes a third electrical connecting terminal for outputting a setting signal based on the characteristic information preset in the characteristic setting unit, and the characteristic setting unit is connected at least between the third and first electrical connecting terminals or between the third and second electrical connecting terminals, and the characteristic setting unit responds to a set-up power inputted from the third electrical connecting terminal to generate the setting signal.

Abstract: As a control parameter given to a direct-current (DC) voltage generator which generates a DC voltage for ion selection, a “mass-related offset” for allowing an adjustment of the offset for each mass-to-charge ratio is provided in addition to the “gain” and “common offset” which respectively determine the gradient and position of a scan line drawn on a stability diagram during a mass-scan operation. In an automatic adjustment operation using a standard sample, under the control of an automatic regulator, the “gain” and “common offset” are initially set, after which the “mass-related offset” for each mass-to-charge ratio is determined so that the mass-resolving power will be substantially uniform, and these data are stored in a control data memory. In an analysis of a sample of interest, a quadrupole voltage controller controls the DC voltage generator and a radio-frequency (RF) voltage generator according to the control parameters read from the memory.

Abstract: A battery is provided with a plurality of unit cells each having a tab, a bus bar connecting the tab of one of the plurality of unit cells and the tab of another one of the plurality of unit cells, and a plurality of welding points disposed on a center of gravity of an area, in which the bus bar and the tab are overlapped, or a vicinity thereof, and at least one position of line segments, radiately extending from the center of gravity, or a vicinity thereof, such that the bus bar and the tab are connected to one another at the plurality of welding points.

Abstract: A laminate cell comprises a power generating element formed by sequentially stacking positive electrode plates and negative electrode plates while interposing separators therebetween; a positive tab connected to the positive electrode plates through a plurality of positive leads; a negative tab connected to the negative electrode plates through a plurality of negative leads; and a cell package formed of a metal composite film, the cell package hermetically sealing the power generating element and an electrolyte. According to the laminate cell, the heat capacity of a portion of the positive tab, onto which a plurality of the positive leads are joined, and the heat capacity of a portion of the negative tab, onto which a plurality of the negative leads are joined, are made larger than that of other portions of the positive tab and the negative tab.

Abstract: A battery is provided with a plurality of unit cells each having a tab, a bus bar connecting the tab of one of the plurality of unit cells and the tab of another one of the plurality of unit cells, and a plurality of welding points disposed on a center of gravity of an area, in which the bus bar and the tab are overlapped, or a vicinity thereof, and at least one position of line segments, radiately extending from the center of gravity, or a vicinity thereof, such that the bus bar and the tab are connected to one another at the plurality of welding points.

Abstract: A digital amplifier comprises: a switching unit that amplifies a signal input to the digital amplifier by performing a switching operation; a driving unit that turns the switching unit on and off; an input signal detection unit that detects an input signal to the digital amplifier; and a first control unit that performs control such that the switching unit starts a switching operation by starting driving of the driving unit, when the digital amplifier is changed to a signal input state and the input signal detection unit detects an input signal, and performs control such that the switching unit stops the switching operation by stopping the driving of the driving unit, when the digital amplifier is changed to a no signal input state and the input signal detection unit does not detect an input signal. This configuration enables to reduce power consumption when no signal is input.

Abstract: A replacement data storage circuit stores an address of a defective memory cell. The replacement data storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of replacement data memory cells. The replacement data memory cells are connected to the word lines and the bit lines to store an address of a defective memory cell. Each of the word lines is connected to a plurality of replacement data memory cells and each of the bit lines is connected to one replacement data memory cell.

Abstract: A light source module includes a substrate unit for mounting multiple light emitting diodes thereon to electrically connecting them; first and second electrical connecting terminals for supplying a current to the light emitting diodes based on a voltage applied from outside the substrate unit; and a characteristic setting unit for presetting characteristic information corresponding to a electrical characteristic of the light emitting diodes. Further, the light source module includes a third electrical connecting terminal for outputting a setting signal based on the characteristic information preset in the characteristic setting unit, and the characteristic setting unit is connected at least between the third and first electrical connecting terminals or between the third and second electrical connecting terminals, and the characteristic setting unit responds to a set-up power inputted from the third electrical connecting terminal to generate the setting signal.

Abstract: A clock recovery apparatus for generating a recovery clock from received data may include, but is not limited to, first and second oscillators. The first oscillator generates a first signal having a first frequency. The first signal synchronizes with the received data when the received data has a first level. The second oscillator is connected in series to the first oscillator. The second oscillator generates a second signal as the recovery clock when the first signal has a second level. The second signal has a second frequency. The second signal synchronizes with the first signal.

Abstract: A flow cell 1 is provided with a flow channel 2 which has rounded corners 3 in section. A measuring sample under high pressure is introduced into the flow channel 2 formed in the flow cell 1 and particles existing in the measuring sample are measured. The measuring sample is in a liquid phase, a gaseous phase or a super critical phase above 1 MPa.

Abstract: A non-volatile semiconductor storage device, includes a memory array including memory cells, a plurality of word lines installed in the memory array, a sub-decoder including a pull-up power line, a pull-down power line and a plurality of drivers, a pre-decoder coupled to the sub-decoder, and generating a pre-decode signal; and a main decoder coupled to the sub-decoder, and generating a main decode signal. A potential of the pull-up power line and a potential of the pull-down power line are controlled in response to the main decode signal. The plurality of drivers drives the plurality of word lines in response to the pre-decode signal.

Abstract: A nonvolatile semiconductor memory device in accordance with the present invention is provided with a plurality of memory cells of field effect transistor type, a source bias control circuit, and a drain bias control circuit. The source bias control circuit variably sets the potential of a source line connected in common to the sources of the plurality of memory cells at the time of write operation. The drain bias control circuit variably sets the potential of the drains of the plurality of memory cells at the time of write operation according to the potential of the source line.

Abstract: A laminate cell comprises a power generating element formed by sequentially stacking positive electrode plates and negative electrode plates while interposing separators therebetween; a positive tab connected to the positive electrode plates through a plurality of positive leads; a negative tab connected to the negative electrode plates through a plurality of negative leads; and a cell package formed of a metal composite film, the cell package hermetically sealing the power generating element and an electrolyte. According to the laminate cell, the heat capacity of a portion of the positive tab, onto which a plurality of the positive leads are joined, and the heat capacity of a portion of the negative tab, onto which a plurality of the negative leads are joined, are made larger than that of other portions of the positive tab and the negative tab.

Abstract: A laminate cell comprises a power generating element formed by sequentially stacking positive electrode plates and negative electrode plates while interposing separators therebetween; a positive tab connected to the positive electrode plates through a plurality of positive leads; a negative tab connected to the negative electrode plates through a plurality of negative leads; and a cell package formed of a metal composite film, the cell package hermetically sealing the power generating element and an electrolyte. According to the laminate cell, the heat capacity of a portion of the positive tab, onto which a plurality of the positive leads are joined, and the heat capacity of a portion of the negative tab, onto which a plurality of the negative leads are joined, are made larger than that of other portions of the positive tab and the negative tab.

Abstract: A replacement data storage circuit stores an address of a defective memory cell. The replacement data storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of replacement data memory cells. The replacement data memory cells are connected to the word lines and the bit lines to store an address of a defective memory cell. Each of the word lines is connected to a plurality of replacement data memory cells and each of the bit lines is connected to one replacement data memory cell.

Abstract: A clock reproducing apparatus includes a clock reproducing circuit having: a gated oscillator having an oscillating circuit of two routes; and a frequency control circuit for comparing a phase of an output of the gated oscillator with a phase of a reference clock, and supplying a phase control signal to the gated oscillator based on the comparison result so as to set a delay time, input data is input to a reset input terminal of the gated oscillator, and different route of the two routes of the oscillating circuit operates depending on a case where the input data is “H” and a case where the input data is “L”.

Abstract: A clock reproducing apparatus includes a clock reproducing circuit having: a gated oscillator having an oscillating circuit of two routes; and a frequency control circuit for comparing a phase of an output of the gated oscillator with a phase of a reference clock, and supplying a phase control signal to the gated oscillator based on the comparison result so as to set a delay time, input data is input to a reset input terminal of the gated oscillator, and different route of the two routes of the oscillating circuit operates depending on a case where the input data is “H” and a case where the input data is “L”.

Abstract: In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the selection memory cells, a gate voltage which increases step by step, until a threshold voltage of each of the selection memory cells reaches a target threshold voltage, such that the threshold voltage increases step-by-step.

Abstract: A nonvolatile semiconductor memory device includes a memory array and an X-decode section. The memory array includes a plurality of nonvolatile memory cells arranged in a matrix form and a plurality of word lines. The X-decode section selects a selected word line selected from the plurality of word lines, supplies a negative voltage to the selected word line, and supplies a positive voltage to unselected word lines which are not the selected word line, at the time of an erase operation.

Abstract: A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit configured to includes fuses and anti-fuses integrated; an address switching circuit configured to produce a second internal address on the basis of the first internal address; and a decoder circuit configured to select a memory cell of the memory array in response to the second internal address. The internal address supplying unit is configured to be capable of fixing a specific address bit in the first internal address. The second internal address includes: fuse independent address bits produced from address bits which is not the specific address bit in the first internal address, independently of a state of the first fuse unit, and a fuse dependent address bit having a value corresponding to the state of the first fuse unit and a vale of the specific address bit.