Patents by Inventor Hiroshi Sukegawa

Hiroshi Sukegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9299438
    Abstract: According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: March 29, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tokumasa Hara, Naoya Tokiwa, Hiroshi Sukegawa, Hitoshi Iwai, Toshifumi Shano, Shirou Fujita
  • Publication number: 20160077913
    Abstract: According to an embodiment, The control method includes reading a plurality of first pages in parallel on the basis of respectively different operation parameters. each of the first pages is respectively included in a plurality of first blocks. Each of the operation parameters includes a read voltage. The control method includes performing error correction on each of read data, and selecting one operation parameter out of the plurality of different operation parameters based on a result of the error correction.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi YAO, Hiroshi SUKEGAWA, Tokumasa HARA
  • Publication number: 20160049204
    Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.
    Type: Application
    Filed: March 3, 2015
    Publication date: February 18, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daiki WATANABE, Hiroshi Sukegawa, Hiroshi Yao, Tokumasa Hara, Naomi Takeda
  • Patent number: 9235751
    Abstract: According to one embodiment, a person image processing apparatus includes: an input processor configured to input a plurality of pieces of image data captured at different times by an image capture module; an extraction module configured to extract a person display area showing a same person from each of the pieces of image data captured at the different times; a feature detector configured to detect a feature point showing a feature of a part of a person from the person display area extracted from each of the pieces of image data and acquire reliability of the part shown in the feature point; and a correction module configured to, when correcting the person display area subjected to input processing by the input processor, perform weighting based on the reliability of the feature point included in the person display area.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Osamu Yamaguchi
  • Patent number: 9229851
    Abstract: A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: January 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Hidetaka Tsuji, Shuji Takano
  • Publication number: 20150380097
    Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.
    Type: Application
    Filed: September 2, 2015
    Publication date: December 31, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu SATO, Daiki WATANABE, Hiroshi SUKEGAWA, Tokumasa HARA, Hiroshi YAO, Naomi TAKEDA, Noboru SHIBATA, Takahiro SHIMIZU
  • Patent number: 9183000
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 10, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Ichida, Hiroshi Sukegawa, Naohiro Matsukawa
  • Patent number: 9177661
    Abstract: According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 3, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tokumasa Hara, Naoya Tokiwa, Hiroshi Sukegawa, Hitoshi Iwai, Toshifumi Shano, Shirou Fujita
  • Patent number: 9171012
    Abstract: According to one embodiment, a facial image search system including, search module configured to calculate degree of similarity between facial features extracted by feature extraction module and facial features contained in database and output search result based on calculated degree of similarity, measuring module configured to measure amount of search result output by search module, and selection module configured to sort out search result output by search module if amount of search result measured by measuring module is equal to or more than preset threshold.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 27, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroo Saito, Hiroshi Sukegawa, Osamu Yamaguchi, Toshio Sato
  • Publication number: 20150248322
    Abstract: According to one embodiment, a memory controller includes a controller that is configured to, when notified of an error by one of memory chips at a time of power supply startup, transmit a first command including an address to the memory chip by which the error was notified, when notified of a normal end by the memory chip in which the first command was received, transmit a second command including an address to the memory chip by which the normal end was notified.
    Type: Application
    Filed: July 24, 2014
    Publication date: September 3, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa Hara, Hitoshi Iwai, Naoya Tokiwa, Toshikatsu Hida, Yoshihisa Kojima, Hiroshi Sukegawa, Shirou Fujita
  • Publication number: 20150248330
    Abstract: A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal, the first data written to the other of the memory cell arrays may be deleted or nullified.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi SUKEGAWA
  • Publication number: 20150234752
    Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 20, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toru KAMBAYASHI, Akihiro KASAHARA, Shinichi MATSUKAWA, Hiroyuki SAKAMOTO, Taku KATO, Hiroshi SUKEGAWA, Yoshihiko HIROSE, Atsushi SHIMBO, Koichi FUJISAKI
  • Patent number: 9098760
    Abstract: According to one embodiment, a face recognizing apparatus includes: a storage unit; an input unit; a face detector; an extractor; and a recognizing unit. The storage unit stores face feature information on a face feature of each person. The input unit receives image information including at least a face of a person. The face detector detects a face region of the face of the person from the image information received by the input unit. The extractor extracts face feature information on a face feature from the face region detected by the face detector. The recognizing unit recognizes the person in the image information received by the input unit based on the feature information extracted by the extracting unit and the face feature information stored in the storage unit.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 4, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroo Saito, Hiroshi Sukegawa, Osamu Yamaguchi
  • Publication number: 20150206590
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group.
    Type: Application
    Filed: August 20, 2014
    Publication date: July 23, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Haruka SAKUMA, Yoshiaki Fukuzumi, Hideaki Aochi, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Shirou Fujita, Ikuo Magaki, Kiwamu Sakuma, Masumi Saitoh
  • Publication number: 20150193301
    Abstract: A controller according to one embodiment controls a memory, the memory including blocks and configured to erase data in the blocks with each of the blocks as a minimum unit. Each of the blocks includes unit memory areas each specified by an address. The controller is configured to add a code for error correction to received data to generate a data unit, divide the data unit into data unit sections, and write the data unit sections in unit memory areas of respective blocks, the unit memory areas having different addresses.
    Type: Application
    Filed: August 27, 2014
    Publication date: July 9, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Naomi Takeda, Hiroshi Yao
  • Patent number: 9063903
    Abstract: A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal or is correctable, the first data written to the other of the memory cell arrays may be deleted or nullified.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 23, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Sukegawa
  • Patent number: 9053062
    Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: June 9, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru Kambayashi, Akihiro Kasahara, Shinichi Matsukawa, Hiroyuki Sakamoto, Taku Kato, Hiroshi Sukegawa, Yoshihiko Hirose, Atsushi Shimbo, Koichi Fujisaki
  • Publication number: 20150138885
    Abstract: A non-volatile semiconductor storage device includes a memory cell array divided into blocks, each of which is a erasable unit, the blocks, the blocks including a first block which is determined to be a bad block and a second block which is determined to be a partial bad block, a storage unit configured to store address information of the first block and the second block, and a block decoder including a latch section which is configured to control selection and non-selection of the blocks, and to release data held by the latch section based on the stored address information of the second block.
    Type: Application
    Filed: February 26, 2014
    Publication date: May 21, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hitoshi IWAI, Hiroshi SUKEGAWA, Naoya TOKIWA
  • Publication number: 20150109862
    Abstract: A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns, and a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns. The first memory connection portion is formed in a first layer of the substrate and the second memory connection portion is formed in a second layer of the substrate that is lower than the first layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: April 23, 2015
    Inventors: Noboru SHIBATA, Hiroshi SUKEGAWA
  • Publication number: 20150113632
    Abstract: According to one embodiment, an identity authentication system includes a detecting unit that detects an identity theft by determining whether a photographing target is a living body or a non-living body, a collating unit that performs identity collation based on a photographed image, and a control unit that controls execution timing of a detection process performed by the detecting unit and an identity collating processing performed by the collating unit and, in a case where the detection performed by the detecting unit is performed for a first number of times, performs the collation process performed by the collating unit, wherein the first number of times is set in consideration of a tradeoff between a required intensity of security and convenience of a user using the identity authentication system.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 23, 2015
    Inventors: Hiroo Saito, Hiroshi Sukegawa