Abstract: A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first word line coupled to gates of the first and third memory cell transistors; and a second word line coupled to gates of the second and fourth memory cell transistors. When the first string unit is selected and the first word line is selected, a first voltage is applied. The first voltage is larger than an initial value of the voltage in the step-up operation.

Abstract: Data are refreshed in a nonvolatile solid-state device to significantly reduce the likelihood of data retention errors. Test data are written in a region of the nonvolatile solid-state device when user data are stored in the nonvolatile solid-state device, and are subsequently read to detect the possibility of data retention errors occurring when the associated user data are read. The test data may be a portion of the user data or a predetermined test pattern. To increase sensitivity to incipient charge leakage that may compromise the user data, the test data may be written using a modified write process and/or read with a modified read operation. The nonvolatile solid-state device may be employed as part of a solid-state drive or as the flash-memory portion of a hybrid hard disk drive.

Abstract: A person recognition apparatus is disclosed that includes an image input unit, a face detection unit in which a face is expressed from the inputted image data, as a score which takes a value in accordance with facial likeness, a facial feature point detection unit, a feature extraction unit, a feature data administrative unit, a person identification unit to calculate similarity between the amount calculated by the feature extraction unit and the amount stored in the feature data administrative unit, a number of candidates calculation unit which displays the images stored in descending order of the similarity, and calculates a score from the face detection unit and the facial feature point detection unit, a candidate confirmation unit in which images displayed in descending order of the similarity are subjected to visual inspection.

Abstract: Data are refreshed in a nonvolatile solid-state device to significantly reduce the likelihood of data retention errors. Test data are written in a region of the nonvolatile solid-state device when user data are stored in the nonvolatile solid-state device, and are subsequently read to detect the possibility of data retention errors occurring when the associated user data are read. The test data may be a portion of the user data or a predetermined test pattern. To increase sensitivity to incipient charge leakage that may compromise the user data, the test data may be written using a modified write process and/or read with a modified read operation. The nonvolatile solid-state device may be employed as part of a solid-state drive or as the flash-memory portion of a hybrid hard disk drive.

Abstract: A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns, and a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns. The first memory connection portion is formed in a first layer of the substrate and the second memory connection portion is formed in a second layer of the substrate that is lower than the first layer.

Abstract: According to one embodiment, an apparatus includes input unit, detecting unit, extraction unit, storage, selection unit, determination unit, output unit, and setting unit. The selection unit selects operation or setting modes. In operation mode, it is determined whether captured person is preregistered person. In setting mode, threshold for the determination is set. The determination unit determines, as registered person and when operation mode is selected, person with degree of similarity between extracted facial feature information and stored facial feature information of greater than or equal to threshold. The setting unit sets, when setting mode is selected, threshold based on first and second degrees of similarity. First degree of similarity is degree of similarity between facial feature information of the registered person and the stored facial feature information.

Abstract: A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first word line coupled to gates of the first and third memory cell transistors; and a second word line coupled to gates of the second and fourth memory cell transistors. When the first string unit is selected and the first word line is selected, a first voltage is applied. The first voltage is larger than an initial value of the voltage in the step-up operation.

Abstract: According to one embodiment, a person authentication method includes obtaining, from a medium carried by a person who passes through a first position, first information indicating the gender and the age of the person; performing a first authentication operation with respect to a person whose face image is included in a first image obtained by capturing a person passing through the first position; and setting, as the first authentication operation, an authentication operation to be performed using the face image of a person having the gender and the age specified in the first information.

Abstract: A memory system according to an embodiment includes: a plurality of magnetic nanowires; a read unit configured to read data from the magnetic nanowires; a shift control unit configured to shift domain walls in the magnetic nanowires; and a read control unit configured to cause the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, determine a misalignment in the data when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, and correct the stored data based on the determined misalignment.

Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.

Abstract: A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns, and a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns. The first memory connection portion is formed in a first layer of the substrate and the second memory connection portion is formed in a second layer of the substrate that is lower than the first layer.

Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

Abstract: According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data.

Abstract: According to an embodiment, The control method includes reading a plurality of first pages in parallel on the basis of respectively different operation parameters. each of the first pages is respectively included in a plurality of first blocks. Each of the operation parameters includes a read voltage. The control method includes performing error correction on each of read data, and selecting one operation parameter out of the plurality of different operation parameters based on a result of the error correction.

Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.

Abstract: According to one embodiment, a person image processing apparatus includes: an input processor configured to input a plurality of pieces of image data captured at different times by an image capture module; an extraction module configured to extract a person display area showing a same person from each of the pieces of image data captured at the different times; a feature detector configured to detect a feature point showing a feature of a part of a person from the person display area extracted from each of the pieces of image data and acquire reliability of the part shown in the feature point; and a correction module configured to, when correcting the person display area subjected to input processing by the input processor, perform weighting based on the reliability of the feature point included in the person display area.

Abstract: A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section.