Patents by Inventor Hiroshi Sukegawa

Hiroshi Sukegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150071004
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • Patent number: 8965061
    Abstract: In a person retrieval apparatus, a plurality of extraction processing sections each extract personal biometric information from images taken by a plurality of cameras. A quality determination section determines a quality of each piece of biometric information extracted by the extraction processing sections. A reliability level setting section sets a reliability level to each piece of biometric information on the basis of the quality determined by the quality determination section. The biometric information extracted by the extraction processing sections and the reliability level set by the reliability level setting section are stored in a memory. In this state, in the person retrieval apparatus, the face retrieval section performs person retrieval processing on each piece of biometric information stored in the memory in descending order of the reliability level corresponding to each piece of biometric information.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: February 24, 2015
    Assignee: Kabuhiki Kaisha Toshiba
    Inventors: Mitsutake Hasebe, Hiroshi Sukegawa, Kei Takizawa, Yasuhiro Aoki
  • Publication number: 20150036430
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Application
    Filed: March 7, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Publication number: 20150039921
    Abstract: A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi SUKEGAWA
  • Publication number: 20150036434
    Abstract: According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data.
    Type: Application
    Filed: December 27, 2013
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Naoya Tokiwa, Hiroshi Sukegawa, Hitoshi Iwai, Toshifumi Shano, Shirou Fujita
  • Publication number: 20140369127
    Abstract: According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data.
    Type: Application
    Filed: September 17, 2013
    Publication date: December 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Naoya Tokiwa, Hiroshi Sukegawa, Hitoshi Iwai, Toshifumi Shano, Shirou Fujita
  • Patent number: 8908433
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • Patent number: 8902670
    Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa Hara, Hiroshi Sukegawa, Toshio Fujisawa, Shirou Fujita, Masaki Unno, Masanobu Shirakawa
  • Patent number: 8902657
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Iwai, Shirou Fujita, Hiroshi Sukegawa, Toshio Fujisawa, Tokumasa Hara
  • Patent number: 8892917
    Abstract: A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Sukegawa
  • Patent number: 8861801
    Abstract: According to one embodiment, a facial image search system including attribute discrimination module configured to discriminate attribute based on facial feature extracted, a plurality of search modules configured to store facial feature as database in advance, add facial feature extracted to database, calculate degree of similarity between facial feature extracted and facial feature contained in database, setting module configured to generate setting information by associating with any attribute with information indicating search module, and control module configured to identify one or a plurality of search modules based on setting information and attribute and transmit facial feature extracted by feature extraction module to identified search modules.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Osamu Yamaguchi
  • Publication number: 20140298043
    Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 2, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toro Kambayashi, Akihiro Kasahara, Shinichi Matsukawa, Hiroyuki Sakamoto, Taku Kato, Hiroshi Sukegawa, Yoshihiko Hirose, Atsushi Shimbo, Koichi Fujisaki
  • Publication number: 20140281157
    Abstract: According to one embodiment, a memory system includes a plurality of non-volatile memory chips and a memory controller. The memory controller controls a read operation of the memory chips, and manages correspondence relation information between a logical address included in a read command and a physical address of the memory chip. The memory controller causes at least two memory chips to store the same correspondence relation information. Further, in the read operation, the memory controller reads the correspondence relation information from at least one memory chip among the plurality of memory chips storing the same correspondence relation information.
    Type: Application
    Filed: July 15, 2013
    Publication date: September 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Iwai, Hiroshi Yao, Hiroshi Sukegawa, Yu Nakanishi
  • Publication number: 20140270370
    Abstract: A person recognition apparatus is disclosed that includes an image input unit, a face detection unit in which a face is expressed from the inputted image data, as a score which takes a value in accordance with facial likeness, a facial feature point detection unit, a feature extraction unit, a feature data administrative unit, a person identification unit to calculate similarity between the amount calculated by the feature extraction unit and the amount stored in the feature data administrative unit, a number of candidates calculation unit which displays the images stored in descending order of the similarity, and calculates a score from the face detection unit and the facial feature point detection unit, a candidate confirmation unit in which images displayed in descending order of the similarity are subjected to visual inspection.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroo Saito, Hiroshi Sukegawa
  • Patent number: 8788907
    Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Kambayashi, Akihiro Kasahara, Shinichi Matsukawa, Hiroyuki Sakamoto, Taku Kato, Hiroshi Sukegawa, Yoshihiko Hirose, Atsushi Shimbo, Koichi Fujisaki
  • Patent number: 8730741
    Abstract: According to one embodiment, a semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device, and a wiring line. The wiring line is connected between the first semiconductor memory device and the second semiconductor memory device. When one of the first and second semiconductor memory devices discharges electric charge, the other of the first and second semiconductor memory devices receives the discharged electric charge through the wiring line.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Shibata, Hiroshi Sukegawa, Tokumasa Hara
  • Publication number: 20140079299
    Abstract: According to one embodiment, an apparatus includes input unit, detecting unit, extraction unit, storage, selection unit, determination unit, output unit, and setting unit. The selection unit selects operation or setting modes. In operation mode, it is determined whether captured person is preregistered person. In setting mode, threshold for the determination is set. The determination unit determines, as registered person and when operation mode is selected, person with degree of similarity between extracted facial feature information and stored facial feature information of greater than or equal to threshold. The setting unit sets, when setting mode is selected, threshold based on first and second degrees of similarity. First degree of similarity is degree of similarity between facial feature information of the registered person and the stored facial feature information.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Hiroo Saito
  • Publication number: 20140071756
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hitoshi Iwai, Shirou Fujita, Hiroshi Sukegawa, Toshio Fujisawa, Tokumasa Hara
  • Publication number: 20140063973
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru SHIBATA, Hiroshi Sukegawa
  • Publication number: 20140063952
    Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Hiroshi Sukegawa, Toshio Fujisawa, Shirou Fujita, Masaki Unno, Masanobu Shirakawa