Abstract: Disclosed is a digital-to-analog converting circuit including: a reference voltage generating circuit for outputting a plurality of reference voltages having voltage values that differ from one another; a data input control circuit for exercising control based upon a control signal so as to output either one of even-numbered bits or odd-numbered bits and then the other of the even-numbered bits or odd-numbered bits from a multiple-bit digital data signal input thereto; a decoder for successively selecting first and second voltages, inclusive of voltages that are identical, from among the plurality of reference voltages, which are output from the reference voltage generating circuit, in accordance with an output signal from the data input control circuit, and outputting the selected first and second voltages successively to the single terminal; and a differential amplifier, receiving the first and second voltages output from the decoder successively from the single terminal, for outputting from an output termi

Abstract: Offset canceling amplifier circuit in which a high accuracy of output with a suppressed output offset is achieved and a variation in a slew rate is also suppressed, and a display device having the amplifier circuit. A first differential pair (M5, M6) connected between a first current source (M9) and a common load circuit (M1, M2) and a second differential pair (M3, M4) connected between a second current source (M8) between the common load circuit (M1, M2) are provided. A switch (SW1) connected between one input of the first differential pair (M5, M6) and an input terminal (1), a switch (SW2) connected between the one input of the differential pair (M5, M6) and an output terminal (2), a switch (SW3) connected between one input of the second differential pair (M3, M4) and the output terminal (2), and a capacitance element (C1) connected to the one input of the second differential pair (M3, M4) are provided.

Abstract: The amplifier includes first and second inverters that form a flip-flop. In this flip-flop, an input of first inverter is connected to an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter. Control terminals of at least one transistors (MN1, MN2) of first and second transistor pairs (MP1, MN1 and MP2, MN2) that constitute first and second inverters, respectively, are connected to inputs of first and second inverters through first and second capacitances (C1, C2), respectively. At resetting, inputs (1, 2) and outputs (OUT, OUTB) of first and second inverters are not mutually cross-connected, wherein a reference signal (VR) is supplied in common to inputs (1, 2) of the first and second inverters. The one transistors (MN1, MN2) are diode-connected. Voltage differences between reference signal (VR) and respective control terminals of the one transistors are stored in the first and second capacitances (C1, C2), respectively.

Abstract: When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

Abstract: A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal.

Abstract: A differential amplifying circuit capable of reducing amplitude-difference deviation over a full range of grayscale voltages inclusive of voltages in the vicinity of power-supply voltage includes first and second differential pairs of mutually different polarities, in which the outputs of the differential pairs are coupled by a coupling stage. One of the first and second differential pairs receives an input signal from an input terminal and a feedback signal from an output terminal at a pair of inputs thereof, and the other differential pair receives reference signals (which may be of the same voltage), which have voltage levels that set the other differential pair transistors to an on-state, at a pair of inputs of the other differential pair.

Abstract: A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

Abstract: A level shift circuit operates normally when amplitude of input signal is small and amplitude of output signal is large. First and second terminals receive an input signal and its complementary signal having a first amplitude. Third and fourth terminals output an output signal and its complementary signal having a second amplitude, which is larger than the first amplitude. Output circuit comprises first and second transistors of first polarity respectively connected between first power supply and fourth and third terminals, respectively. Third and fourth transistors of second polarity, respectively, are connected between second power supply and fourth and third terminals, respectively, having control ends connected to the third and the fourth terminals, respectively. First current control circuit controls so that a current driving the fourth terminal flows through the first transistor according to the input signal and the complementary signal of the output signal.

Abstract: Disclosed is a digital-to-analog converter including a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n?1:2n?2: . . . :20, from an output terminal.

Abstract: When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

Abstract: A selection circuit receives a plural number (m) of respective different values of voltages as reference voltages to select and output two voltages.

Abstract: Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input te

Abstract: Disclosed is a multi-level output differential amplifier which includes a first differential pair; a second differential pair; a load circuit commonly connected to output pairs of the first and second differential pairs; first and second current sources for supplying current to the first and second differential pairs, respectively; an amplifier stage for receiving a common output signal of the first and second differential pairs and driving an output terminal by a charging or discharging operation; and a control circuit for controlling changeover of signal inputs to the first and second differential pairs. The data output period includes first and second time periods.

Abstract: A driving circuit for driving a capacitive load promptly to a target voltage is to have a broad dynamic range and achieve a high accuracy output and saving in the surface area with low power dissipation. A first period and a second period are provided in one data driving period. During the first period, a transistor amplifier for driving the load for charging, with a setting drive voltage (V1), and a transistor amplifier for driving the load for discharging, with a setting drive voltage (V2), with V1<V2, are both enabled for actuation and, during the second period, the transistor amplifier performing either the driving for charging or the driving for discharging, and a constant current source, performing the reverse of the operation of the transistor amplifier, are actuated, for driving the load to the target voltage.

Abstract: A differential amplifier includes a differential amplifying stage and an output amplifying stage. The output amplifying stage includes a first transistor for pull-up, a second transistor for pull-down, a capacitor element, and switches. The first transistor for pull-up is connected across an output terminal and a high potential side power supply VDD and has a control terminal to which is connected a first differential output. The second transistor for pull-down is connected across the output terminal and a low potential side power supply VSS and has a control terminal to which is connected a second differential output. The switches interchangeably connect the capacitor element across the output terminal and the control terminal of the first transistor for pull-up or across the output terminal and the control terminal of the second transistor for pull-down.

Abstract: A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair.

Abstract: Disclosed is a digital-to-analog converting circuit including: a reference voltage generating circuit for outputting a plurality of reference voltages having voltage values that differ from one another; a data input control circuit for exercising control based upon a control signal so as to output either one of even-numbered bits or odd-numbered bits and then the other of the even-numbered bits or odd-numbered bits from a multiple-bit digital data signal input thereto; a decoder for successively selecting first and second voltages, inclusive of voltages that are identical, from among the plurality of reference voltages, which are output from the reference voltage generating circuit, in accordance with an output signal from the data input control circuit, and outputting the selected first and second voltages successively to the single terminal; and a differential amplifier, receiving the first and second voltages output from the decoder successively from the single terminal, for outputting from an output termi

Abstract: In a mobile phone having a liquid crystal display unit, the entire liquid crystal display unit is displayed in a simple display mode at lest in a non-operating standby mode. In the simple display mode, the entire liquid crystal display unit is driven by reducing the number of gradation levels or by decreasing a liquid crystal driving voltage. By using such a controlling method, the power consumption of the liquid crystal display unit can be reduced in the non-operating standby mode. On the other hand, necessary information such as time and the amount of remaining battery is displayed such that the information can be read.

Abstract: Disclosed is a display device including display unit, a column driver, a delay control circuit, an output switch control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of data lines and a plurality of scan lines in a matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan signal to each of the scan line in a preset scan cycle.

Abstract: Disclosed is a differential amplifier which comprises first and second terminals for receiving signals; a third terminal for outputting a signal; first and second differential pairs, each having an input pair and an output pair, said first and second differential pairs being supplied with currents from associated current sources, respectively; a load circuit connected to output pairs of said first and second differential pairs; an amplifier stage for receiving, as an input, a signal of at least one connection node of a connection node pair of said load circuit and output pairs of said first and second differential pairs, said amplifier stage having an output connected to said third terminal; and a connection switching circuit for controlling the switching between a first connection state in which first and second inputs of the input pair of said first differential pair are connected to said first and second terminals, respectively, and in which first and second inputs of the input pair of said second differen