Patents by Inventor Hiroshi Tsuchi

Hiroshi Tsuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100052966
    Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.
    Type: Application
    Filed: November 11, 2009
    Publication date: March 4, 2010
    Inventor: Hiroshi Tsuchi
  • Patent number: 7667538
    Abstract: A differential amplifier comprises terminals for receiving signals, and outputting a signal, and differential pairs, each having an input and output pair, the differential pairs supplied with currents, respectively, a load circuit connected to the differential pairs, an amplifier stage for receiving input, a signal of at least one connection node of the load circuit and output pairs of the differential pairs, the amplifier stage having an output connected to a terminal and a connection switching circuit for controlling switching between connection states of a first differential pair and second differential pair.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: February 23, 2010
    Assignee: NEC Corporation
    Inventor: Hiroshi Tsuchi
  • Publication number: 20100013686
    Abstract: Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 21, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroshi Tsuchi
  • Patent number: 7639167
    Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: December 29, 2009
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Publication number: 20090295767
    Abstract: Disclosed is a digital-to-analog converter in which a plurality of reference voltages that differ from one another are grouped into first to (S+1)th reference voltage groups. The digital-to-analog converter has a decoder and an amplifying circuit. The decoder includes: first to (S+1)th subdecoders for selecting respective ones of reference voltages corresponding to a value of a first bit group on an upper bit side of an input digital signal from the reference voltages of the first to (S+1)th reference voltage groups; and an (S+1)-input and 2-output type subdecoder for selecting and outputting two reference voltages out of reference voltages selected by the first to (S+1)th subdecoders, in accordance with a value of a second bit group on a lower side of the input digital signal.
    Type: Application
    Filed: May 22, 2009
    Publication date: December 3, 2009
    Applicant: NEC ELECTRONICS CORPORTION
    Inventor: Hiroshi Tsuchi
  • Patent number: 7623054
    Abstract: Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input te
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: November 24, 2009
    Assignee: NEC Corporation
    Inventors: Masao Iriguchi, Hiroshi Tsuchi
  • Patent number: 7619445
    Abstract: A differential amplifier includes a first differential pair, a second differential pair, a load circuit, connected in common to the first and second differential pairs, and first and second current sources for supplying the current to the first and second differential pairs, and amplifies a signal responsive to a common output signal of the first and second differential pairs. One of differential inputs of the first differential pair is connected to a reference voltage. A data output period includes a first period and a second period. During the first period, voltages of first and second input terminals are input through first and fourth switches in the on-state to differential inputs of the second differential pair. The other of the differential inputs of the first differential pair is connected through a third switch in the on-state to an output terminal. An output voltage is stored in a capacitor C connected to the other differential input of the first differential pair.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: November 17, 2009
    Assignee: NEC Corporation
    Inventor: Hiroshi Tsuchi
  • Publication number: 20090278868
    Abstract: To obtain an amplifier circuit capable of realizing low power consumption and high-precision output. A controlling unit controls each switch of an offset correction circuit to select one capacitor associated with a voltage level of an input signal selected by an input signal selection unit, have an offset voltage of an operational amplifier generated according to the voltage level of the input signal stored by the selected capacitor, and correct an output of the operational amplifier by using the offset voltage held by the selected capacitor.
    Type: Application
    Filed: July 17, 2009
    Publication date: November 12, 2009
    Applicant: NEC CORPORATION
    Inventors: Yoshihiko NAKAHIRA, Hiroshi TSUCHI
  • Publication number: 20090273618
    Abstract: A data driver having a positive-polarity reference voltage generation circuit, a positive-polarity decoder, a first amplifier that outputs a positive-polarity gray scale voltage, a negative-polarity reference voltage generation circuit that generates a plurality of negative-polarity reference voltages, a negative-polarity decoder that outputs first to nth negative-polarity reference voltages from among the negative-polarity reference voltages, a negative-polarity amplifier that receives the selected first to nth negative-polarity reference voltages and outputs a negative-polarity gray scale voltage, and an output switch circuit that switches and controls whether to directly connect the first output terminal and the second output terminal to first and second data lines, respectively, or to cross-connect the first output terminal and the second output terminal to the second data line and the first data line, respectively, based on a control signal.
    Type: Application
    Filed: July 8, 2009
    Publication date: November 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroshi Tsuchi
  • Publication number: 20090244056
    Abstract: Disclosed is an output amplifier circuit including a differential stage, a first output stage that receives outputs of the differential stage, and a second output stage having an output thereof electrically connected to a load. The differential stage receives an input signal at a non-inverting input thereof. In the first connection configuration, an output of the first output stage is electrically disconnected from the output of the second output stage, outputs of the differential stage are electrically disconnected from inputs of the second output stage, and a second input of the differential stage is electrically connected to the output of the first output stage. In the second connection configuration, the output of the first output stage is electrically connected to the output of the second output stage, and the outputs of the differential stage is electrically connected to the inputs of the second output stage.
    Type: Application
    Filed: March 30, 2009
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi TSUCHI
  • Patent number: 7595533
    Abstract: When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: September 29, 2009
    Assignee: NEC Corporation
    Inventors: Kenji Sera, Hiroshi Tsuchi
  • Publication number: 20090231319
    Abstract: Disclosed is a differential amplifier of the present invention includes a differential pair differentially receiving a signal, a current source connected between a first voltage supply and the differential pair, for driving the differential pair, a current-to-voltage converter circuit receiving output currents of the differential pair and producing first and second voltage signals, first and second transistors of mutually different conductivity types connected in series between the first voltage supply and a second voltage supply and respectively receiving the first and second voltage signals at control terminals thereof, a third transistor connected between the second voltage supply and an output terminal and receiving the first voltage signal at a control terminal thereof, and a fourth transistor of the same conductivity type as that of the third transistor, the fourth transistor being connected between the output terminal and the first voltage supply and having a control terminal thereof connected to a con
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi TSUCHI
  • Patent number: 7586504
    Abstract: To obtain an amplifier circuit capable of realizing low power consumption and high-precision output. A controlling unit controls each switch of an offset correction circuit to select one capacitor associated with a voltage level of an input signal selected by an input signal selection unit, have an offset voltage of an operational amplifier generated according to the voltage level of the input signal stored by the selected capacitor, and correct an output of the operational amplifier by using the offset voltage held by the selected capacitor.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: September 8, 2009
    Assignee: NEC Corporation
    Inventors: Yoshihiko Nakahira, Hiroshi Tsuchi
  • Publication number: 20090213051
    Abstract: Disclosed is a digital-to-analog converting circuit (DAC) which in accordance with an m-bit digital signal, selects two reference voltages, inclusive of redundant selection of the same reference voltage (inclusive also of reference voltages other than adjacent voltages) out of a plurality of reference voltages and outputs a voltage level that is the result of interpolation from the two reference voltages. The plurality of reference voltages are grouped into first to (3S+1)th reference voltage groups (where S is an integer that is a power of 2). An ith reference voltage group [where i is 1 to (3S+1)] includes [3S×(j?1)+i]th reference voltages (where j=1, 2, . . . h, and h is a prescribed integer). The DAC has a decoder and an interpolation amplifier.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 27, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroshi Tsuchi
  • Patent number: 7576674
    Abstract: Disclosed is a data driver including a reference voltage generation circuit that generates and outputs a plurality of reference voltages, a decoder circuit that selects from among the reference voltages n (where n is an integer greater than or equal to two) reference voltages inclusive of reference voltages that may be identical and outputs the n reference voltages from n output terminals thereof, and an amplifying circuit that includes n differential circuits, a feedback resistor, and a resistor. The n output terminals are connected to non-inverting input terminals of the n differential circuits, respectively. The amplifying circuit outputs an output voltage obtained by operating and synthesizing the n reference voltages. One end of the feedback resistor is connected to an output terminal of the amplifying circuit, and the other end is connected to inverting input terminals of the n differential circuits connected in common.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: August 18, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Publication number: 20090195291
    Abstract: Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 6, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Publication number: 20090184983
    Abstract: A display apparatus includes a display panel; and a display panel driver configured to drive signal lines of the display panel. The display panel driver includes: a color reducing circuit configured to be possible to generate a first color reduction image data from a first input image data by executing an error diffusion process by using a first error value, and to generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value which is different from the first error value; and a driving section configured to drive a first pixel positioned on a horizontal line of the display panel in response to the first color reduction image data, and drive a second pixel positioned on the horizontal line and adjacent to a the first pixel in a horizontal direction, in response to the second color reduction image data.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 23, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Takashi Nose, Hirobumi Furihata, Yoshihiko Hori, Hiroshi Tsuchi
  • Patent number: 7554389
    Abstract: A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 30, 2009
    Assignee: NEC Corporation
    Inventors: Hiroshi Tsuchi, Masao Iriguchi
  • Publication number: 20090160848
    Abstract: Disclosed is a level shift circuit including a first level shift circuit that is connected between a first power supply terminal and first and second output terminals and receives first and second input signals from the first and second input terminals, respectively, and sets one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shift circuit that is connected between a second power supply terminal and the first and second output terminals, and sets the other of the first and second terminals to a second voltage level; and a circuit that performs control to disconnect a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that is driven to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals for a predetermined period including the time point when the first and second input sig
    Type: Application
    Filed: December 18, 2008
    Publication date: June 25, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Patent number: 7545305
    Abstract: A data driver includes a positive-polarity reference voltage generation circuit that outputs positive-polarity reference voltages, a positive-polarity decoder that receives the positive-polarity reference voltages from the positive-polarity reference voltage generation circuit, end selects and outputs at least one positive-polarity reference voltage in accordance with first digital data, a positive-polarity amplifier which includes a first differential units that receives the selected reference voltage selected by the positive-polarity decoder, performs amplification, and outputs a voltage to a first amplifier output terminal, ? negative-polarity reference voltage generation circuit that outputs negative-polarity reference voltages, and a negative-polarity decoder that receives the negative-polarity reference voltages from the negative-polarity reference voltage generation circuit, and selects and outputs at least one negative-polarity reference voltage in accordance with second digital data.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: June 9, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi