Abstract: Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal.

Abstract: Disclosed is a level shift circuit that includes a first transistor of a first conductivity type connected between a first power supply line and a first node, and second and third transistors of a second conductivity type connected in series between a second power supply line and the first node. A first control signal is supplied in common to a gate of the first transistor and a gate of one of the second and third transistors. A gate of the other of the second and third transistors is connected to an input terminal to which an input signal with an amplitude lower than a power supply amplitude of the first and second power supplies is supplied.

Abstract: Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

Abstract: Disclosed is an output circuit including a differential amplifier stage, an output amplifier stage, an amplification acceleration circuit and a capacitance connection control circuit. The output amplifier stage includes push/pull type transistors connected an output terminal. The amplification acceleration circuit includes a first switch and a first transistor, connected between a first output of the differential amplifier stage and the output terminal, and a second transistor and a second switch connected between the output terminal and a second output of the differential amplifier stage. The capacitance connection control circuit includes first capacitive element having first end connected to the output terminal, a first switch connected between a second end of the first capacitive element and a first voltage supply terminal, and a second switch connected between the second end of the first capacitive element and one output of a first differential pair of the differential amplifier stage.

Abstract: A data driver having a positive-polarity reference voltage generation circuit, a positive-polarity decoder, a first amplifier that outputs a positive-polarity gray scale voltage, a negative-polarity reference voltage generation circuit that generates a plurality of negative-polarity reference voltages, a negative-polarity decoder that outputs first to nth negative-polarity reference voltages from among the negative-polarity reference voltages, a negative-polarity amplifier that receives the selected first to nth negative-polarity reference voltages and outputs a negative-polarity gray scale voltage, and an output switch circuit that switches and controls whether to directly connect the first output terminal and the second output terminal to first and second data lines, respectively, or to cross-connect the first output terminal and the second output terminal to the second data line and the first data line, respectively, based on a control signal.

Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.

Abstract: Disclosed is a data receiver circuit including a differential pair having first and second transistors of a first conductivity type, which receives at first and second inputs thereof a binary signal by which data transfer is performed in a differential form, a load circuit composed of first and second diode-connected transistors of a second conductivity type, connected to the first and second inputs of the differential pair, respectively, an output circuit that charges and discharges an output terminal using currents corresponding to currents that flow through the first and second diode-connected transistors of the second conductivity type, respectively, and a current supply circuit with an output current thereof input to at least one of the first and second diode-connected transistors of the second conductivity type.

Abstract: Disclosed is a display device including display unit, a column driver, a delay control circuit, an output switch control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of data lines and a plurality of scan lines in a matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan signal to each of the scan line in a preset scan cycle.

Abstract: An output amplifier includes a differential stage having a reference voltage supplied to a first input, a first output stage that receives an output of the differential stage, a second output stage whose output is connected to a load, a capacitor element having a first end connected to a second input of the differential stage, and connection control circuits that control switching of first and second connection modes. In the first connection mode, there are provided a non-conductive state between output of the differential stage and input of the second output stage, a non-conductive state between output of the first output stage and output of the second output stage, a conductive state between output of the first output stage and the second input of the differential stage, and voltage of a second end of the capacitor element is an input voltage from the input terminal.

Abstract: Disclosed is a data driver including a zero compensation resistor connected in series with a phase compensation capacitor between an output node of an input differential amplification stage and an output node of a succeeding amplification stage, and a control circuit that controls to switch a resistance value of the zero compensation resistor. The control circuit switches the resistance value of the zero compensation resistor to a first resistance value or a second resistance value larger than the first resistance value in response to turning off or on of an output switch that controls connection between the output terminal of an amplifying circuit and a data line.

Abstract: A level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V1) when conducting, a second circuit connected between a second PST and OT to set OT to the second voltage (V2) when conducting, and a third circuit that receives an input signal and a feedback signal from OT so that, when OT=V2 and input=a third voltage (V3), the first circuit conducts, and when OT=V1, the first circuit is made nonconductive irrespective of the value of the input signal. The second circuit is made conductive and nonconductive, when the input=a fourth voltage (V4) and V3, respectively. A high/low relationship of V1, V2=that of V3, V4. The input between V3, V4 has a lower amplitude than the output signal between V1, V2.

Abstract: Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal.

Abstract: Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level.

Abstract: A digital-to-analog converter including includes a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n?1:2n?2: . . . :20, from an output terminal.

Abstract: There is provided a decoder in which a matrix of transistors, a plurality of reference voltage signal lines arranged on a first interconnect layer and extended in a row direction, being separated to one another over the matrix, and a plurality of reference voltage signal lines arranged on a second interconnect layer and extended in the row direction, being separated to one another over the matrix. The reference voltage signal lines on the mutually different layers are respectively connected to impurity diffusion layers of the transistors that are adjacent in the row direction.

Abstract: A digital-to-analog converter circuit includes: a first subdecoder for receiving a first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving a second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving a third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages that have been selected by respective ones of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting a result of an operation applied to the two reference voltages.

Abstract: A selection circuit receives a plural number (m) of respective different values of voltages as reference voltages to select and output two voltages. An amplifier receives at two input terminals the two reference voltages output from the selection circuit to output an output voltage extrapolated.

Abstract: In a mobile phone having a liquid crystal display unit, the entire liquid crystal display unit is displayed in a simple display mode at lest in a non-operating standby mode. In the simple display mode, the entire liquid crystal display unit is driven by reducing the number of gradation levels or by decreasing a liquid crystal driving voltage. By using such a controlling method, the power consumption of the liquid crystal display unit can be reduced in the non-operating standby mode. On the other hand, necessary information such as time and the amount of remaining battery is displayed such that the information can be read.

Abstract: A digital-to-analog converter of reduced number of elements and smaller area includes a reference voltage generating circuit for outputting a plurality of reference voltages having voltage values that differ from one another; a first logic circuit for outputting the result of a logical operation on a first bit group comprising even-numbered bits (or odd-numbered bits) of an input digital data signal composed of a plurality of bits; a second logic circuit for outputting the result of a logical operation on a second bit group comprising the odd-numbered bits (or even-numbered bits) of the input digital data signal composed of the plurality of bits; a switch group circuit for supplying first and second terminals with voltages selected, inclusive of voltages that are identical, from among the plurality of reference voltages, which are output from the reference voltage generating circuit, in accordance with respective outputs from the first and second logic circuits; and an amplifier circuit for outputting an outp

Abstract: Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line.