Patents by Inventor Hiroshi Watanabe

Hiroshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10177923
    Abstract: A network of electronic appliances includes a plurality of network units of electronic appliances. The network units include a first network unit and a plurality of second network units. The first network unit is connected to at least one of the second network units. Each of the network units includes a stem server and a plurality of peripheral devices connected to the stem server. The stem server includes at least one passcode and at least one list of a plurality of registration codes. Each list is associated to a respective passcode. Each registration code of one list associating to one passcode corresponds to a respective peripheral device. Each registration code is generated in response to a respective passcode using physical randomness of a respective peripheral device in correspondence to the passcode. An address of each identification cell is defined by several word lines and bit lines.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Inventor: Hiroshi Watanabe
  • Patent number: 10165147
    Abstract: An image processing apparatus includes a scanner, a communication interface, and a controller. The controller is configured to generate property and setting data of image data that is generated based on image scanning by the scanner, and control the communication interface to transmit the image data and the property and setting data thereof to a server connected to the image processing apparatus through a network, so that the image data and the property and setting data thereof are stored therein in association with each other.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 25, 2018
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Toshihiro Ida, Hiroshi Watanabe, Kazuhiro Ogura, Takahiro Hagiwara, Shinji Makishima, Akihiro Mizutani, Yusuke Hamada, Ken Sakuta
  • Publication number: 20180306597
    Abstract: A vehicular display device includes a display configured to display an image in a display area that overlaps a position of a windshield of a vehicle, a display processor configured to display a direction guide image in the display area in a manner superimposed on a road on which the vehicle is traveling, the direction guide image being an image showing a turn position where the vehicle is to make a turn on the road, and a display pattern determiner configured to determine a display pattern of the direction guide image based on a traveling speed of the vehicle. The display pattern determiner determines the display pattern such that, the higher the traveling speed is, the longer a length from a top end to a bottom end of the direction guide image is.
    Type: Application
    Filed: October 9, 2015
    Publication date: October 25, 2018
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Norio Kosaka, Tetsuya Yamamoto, Hiroshi Watanabe, Masayuki Shishido, Kenji Maruyama
  • Publication number: 20180292229
    Abstract: A front object determiner determines an object on a traveling road surface in front of a host vehicle based on an image of a forward view captured by a front camera. A display controller draws an overlapping portion where a guide route calculated by a navigation device and the object determined by the front object determiner overlap each other in a display region on a windshield and a non-overlapping portion where the guide route and the object do not overlap each other in the display region on the windshield such that the overlapping portion is to be presented in a mode different from a mode for the non-overlapping portion.
    Type: Application
    Filed: September 30, 2015
    Publication date: October 11, 2018
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Kenji Maruyama, Hiroshi Watanabe, Norio Kosaka, Masayuki Shishido
  • Patent number: 10094315
    Abstract: A rotational speed control apparatus for an engine that drives an air conditioning compressor includes an electronic control unit. The electronic control unit corrects a calculated value of a load torque of a compressor in accordance with a deviation between a rotational speed of the engine and a target rotational speed, as a changeover transition period control, in a changeover transition period. The electronic control unit also sets an execution period of the changeover transition period control such that the execution period in a changeover transition period from the stopped state to the driven state of the compressor is longer than an execution period of the changeover transition period control in a changeover transition period from the driven state to the stopped state of the compressor.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: October 9, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroshi Watanabe
  • Patent number: 10090678
    Abstract: A production energy management system is provided, including a production and energy flow model definer configured to define a production and energy flow model wherein the production and energy flow model represents, by directed lines, a flow with regard to an input and output of a production-related material between apparatuses disposed in a plant and a flow with regard to an input and output of energy and associates index values of the production-related material and the energy with a kind of metered data measured in the plant, a data collector configured to collect the metered data from the plant, and an energy calculator configured to perform an energy calculation for each apparatus based on the collected metered data and the defined production and energy flow model.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 2, 2018
    Assignee: Yokogawa Electric Corporation
    Inventors: Tomoyuki Ikeyama, Hiroshi Watanabe, Ken-ichi Inoue, Akira Seki
  • Patent number: 10090675
    Abstract: A power loss protection integrated circuit includes a VIN terminal, a VOUT terminal, an STR terminal, a switch circuit (eFuse), a control circuit, and a prebiasing circuit. In a normal mode, current flows from a power source, into VIN, through the eFuse, out of VOUT, and to the output node. A switching converter of which the control circuit is a part is disabled. If a switch over condition then occurs, the eFuse is turned off and the switching converter starts operating. The switching converter receives energy from STR and drives the output node. Switch over is facilitated by prebiasing. Prior to switch over, the prebiasing circuit prebiases a control loop node as a function of eFuse current flow prior to switch over. When the switching converter begins operating, the node is already prebiased for the proper amount of current to be supplied by the switching converter onto the output node.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 2, 2018
    Assignee: Active-Semi, Inc.
    Inventors: Thuc Huu Lam, Hue Khac Trinh, Hiroshi Watanabe
  • Publication number: 20180270058
    Abstract: An authenticated network having a plurality of nodes is disclosed. Each node includes a transaction unit and an identification core. The identification core includes a key generator. The key generators of the identification cores generate a plurality of unique pairs of secret and public keys. The public key serves as a logical address of the transaction unit. Another authenticated network having a plurality of nodes is also disclosed, in which the identification core further includes a private key. The key generators of the identification cores generate a plurality of public keys from the private keys of the identification cores. Each public key serves as a logical address of the transaction unit of a corresponding node. One of the public keys and one of the private keys form a unique pair. Thus, the transaction unit manages the information communication among the plurality of nodes. The identification core manages an authentication of the nodes.
    Type: Application
    Filed: January 15, 2018
    Publication date: September 20, 2018
    Inventors: Guigen Xia, Hiroshi Watanabe
  • Publication number: 20180259764
    Abstract: A microscope system includes: a stage on which a specimen is mounted; one or more light sources configured to emit light irradiating the specimen; an illumination optical system configured to irradiate the specimen with the light; an operating unit configured to receive selection of the light sources and setting of the state and/or an amount of light; a focusing unit configured to move in a direction orthogonal to a mounting surface and adjust the distance between the stage and an objective lens; an imaging unit configured to image the observation image of the specimen and generate image data; and a combined image generating unit configured to combine the image data and generate combined image data. The microscope system enables selection of the state of optical elements constituting the illumination optical system and selection of the type, the state, and an amount of light of the light source.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 13, 2018
    Applicant: OLYMPUS CORPORATION
    Inventor: Hiroshi WATANABE
  • Publication number: 20180257489
    Abstract: A vehicular display device, in execution of following cruise control with a preceding vehicle ahead of a host vehicle, causes a fixed indication to light up and displays a following mark in a superimposed manner with a following-target preceding vehicle. The fixed indication indicates that the following-target preceding vehicle has been detected. The vehicular display device includes a preceding vehicle detector that detects the following-target preceding vehicle, a display setter that sets the fixed indication to light up and sets the following mark to be displayed in a superimposed manner with the following-target preceding vehicle when the following-target preceding vehicle has been detected by the preceding vehicle detector, and a head-up display that displays images of the fixed indication and the following mark set by the display setter in a display region provided to be superimposed on a position of a windshield of the host vehicle.
    Type: Application
    Filed: September 18, 2015
    Publication date: September 13, 2018
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Hiroshi Watanabe, Masayuki Shishido, Norio Kosaka, Kenji Maruyama
  • Patent number: 10063729
    Abstract: According to one embodiment, there is provided a terminal that includes a memory and a processor. The memory stores authentication-related information indicating that a first cloud completes approval of authentication, which is acquired by a terminal from the first cloud that transmits an instruction to perform a job to a job-performing apparatus of which registration is completed based on an instruction from the terminal, if the registration of the job-performing apparatus is completed. The processor retains the authentication-related information in a storage area if the job-performing apparatus is registered with the first cloud, and, if the authentication-related information is not present in the memory after the approval by the first cloud, acquires the authentication-related information from the storage area.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: August 28, 2018
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Takahiro Hagiwara, Hiroshi Watanabe, Akihiro Mizutani, Toshihiro Ida, Yusuke Hamada, Koji Endo, Kazuhiro Kamimura, Kazuhiro Ogura
  • Patent number: 10062758
    Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: August 28, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
  • Patent number: 10054033
    Abstract: A cooling apparatus includes a coolant circulation channel for returning a coolant that passes through an engine main body, after causing the coolant to exchange heat with a radiator, device(s) and a heater, respectively. A multifunction valve as a rotary valve that is capable of adjusting an amount of coolant that is circulated to the radiator, device(s) and heater, respectively, is disposed in the coolant circulation channel. When automatic stopping of the engine is performed by idle stop-start control, during the automatic stopping the control apparatus continues to execute valve control of the multifunction valve that is being executed during the operation before the start of the automatic stopping.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: August 21, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroshi Watanabe
  • Publication number: 20180232539
    Abstract: A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.
    Type: Application
    Filed: June 30, 2017
    Publication date: August 16, 2018
    Inventors: Hiroshi Watanabe, TAKESHI HAMAMOTO
  • Publication number: 20180234413
    Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures P2P type communication on logical network, to physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.
    Type: Application
    Filed: February 13, 2017
    Publication date: August 16, 2018
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Publication number: 20180227454
    Abstract: According to one embodiment, there is provided a terminal that includes a memory and a processor. The memory stores authentication-related information indicating that a first cloud completes approval of authentication, which is acquired by a terminal from the first cloud that transmits an instruction to perform a job to a job-performing apparatus of which registration is completed based on an instruction from the terminal, if the registration of the job-performing apparatus is completed. The processor retains the authentication-related information in a storage area if the job-performing apparatus is registered with the first cloud, and, if the authentication-related information is not present in the memory after the approval by the first cloud, acquires the authentication-related information from the storage area.
    Type: Application
    Filed: March 17, 2017
    Publication date: August 9, 2018
    Inventors: Takahiro Hagiwara, Hiroshi Watanabe, Akihiro Mizutani, Toshihiro Ida, Yusuke Hamada, Koji Endo, Kazuhiro Kamimura, Kazuhiro Ogura
  • Patent number: 10042591
    Abstract: According to one embodiment, an image forming apparatus includes a processor, a network interface and a display device. The network interface under processor control acquires identification information of a different image forming apparatus on which a user is determined to have use authority based on user identification information of the user. The network interface under processor control also acquires an image forming job registered with the different image forming apparatus based on the acquired identification information of the different image forming apparatus. The display device under processor control displays the image forming job acquired by the network interface.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 7, 2018
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Takahiro Hagiwara, Shinji Makishima, Koji Endo, Hiroshi Watanabe, Akihiro Mizutani, Toshihiro Ida, Yusuke Hamada, Kazuhiro Ogura, Takeo Nishijima
  • Publication number: 20180219091
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 2, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 10036302
    Abstract: A cooling device includes a first cooling medium circuit for circulating a cooling medium that passes through a main body of an engine to a first heat exchanger, a second cooling medium circuit for circulating a cooling medium that passes through the main body to a second heat exchanger, a control valve that is commonly used in the first and second cooling medium circuits, and a control device. The control valve includes a rotatable rotor, and is configured such that a rotation range of the rotor includes a water stop section in which the circuits are both closed. The control device restricts output power of the engine in a period in which the rotation angle is in the water stop section, when the rotor rotates via the water stop section at an operating time of the control valve.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 31, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroshi Watanabe
  • Publication number: 20180212049
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: March 21, 2018
    Publication date: July 26, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe