Patents by Inventor Hiroshi Watanabe

Hiroshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170221581
    Abstract: A semiconductor apparatus including a semiconductor chip is disclosed. The semiconductor chip includes a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses are randomly formed related to a part or a whole of the modular area of the modular region. The test circuit outputs a random number generated from physical properties intrinsic to the semiconductor chip according to a specification code received from a physical-chip-identification measuring device.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 3, 2017
    Inventor: Hiroshi Watanabe
  • Patent number: 9721742
    Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 1, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9705402
    Abstract: A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 11, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9698568
    Abstract: A cathode electrode, cathode pad electrodes, cathode wiring electrodes, an anode electrode, an anode pad electrode, and an anode wiring electrode are disposed on the surface of a vertical-cavity surface-emitting laser device. A light-emitting-region multilayer portion having active layers sandwiched by clad layers and DBR layers is formed directly below the anode electrode. A region where the light-emitting-region multilayer portion is formed serves as a light-emitting region. The light-emitting region is positioned closer to one end of the first direction than is a suction region onto which a flat collet sucks with respect to the first direction, in such a way that the light-emitting region is substantially in contact with or spaced a predetermined distance from the suction region.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: July 4, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiji Iwata, Ippei Matsubara, Takayuki Kona, Hiroshi Watanabe, Masashi Yanagase
  • Patent number: 9679652
    Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 13, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20170162649
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro KAGAWA, Akihiko FURUKAWA, Shiro HINO, Hiroshi WATANABE, Masayuki IMAIZUMI
  • Publication number: 20170143701
    Abstract: Provided is a safe carbohydrate metabolism-ameliorating agent having an excellent carbohydrate metabolism-ameliorating action, and a safe GLP-1 secretion accelerator having an excellent GLP-1 secretion-accelerating action. The carbohydrate metabolism-ameliorating agent or GLP-1 secretion accelerator according to the present invention, which contains a specific cyclic dipeptide or a salt thereof as an active ingredient, is advantageous in that it has an excellent carbohydrate metabolism-ameliorating action, and that it is safe and can be ingested for a long period.
    Type: Application
    Filed: June 11, 2015
    Publication date: May 25, 2017
    Applicant: SUNTORY HOLDINGS LIMITED
    Inventors: Toshihide Suzuki, Kenji Yamamoto, Yoshinori Beppu, Hiroshi Watanabe
  • Patent number: 9650415
    Abstract: A uric acid-lowering agent containing, as an active ingredient, a tyrosine-containing cyclic dipeptide selected from the group consisting of cyclotryptophanyltyrosine, cycloseryltyrosine, cycloprolyltyrosine, cyclotyrosylglycine, cyclotyrosyltyrosine, cyclophenylalanyltyrosine, cycloleucyltyrosine, cyclolysyltyrosine, cyclohistidyltyrosine, cycloalanyltyrosine, cycloglutamyltyrosine, cyclovalyltyrosine, cycloisoleucyltyrosine, cyclothreonyltyrosine, cycloaspartyltyrosine, cycloasparaginyltyrosine, cycloglutaminyltyrosine, cycloarginyltyrosine, cyclomethionyltyrosine, and cyclotyrosylcysteine, or a salt thereof. The uric acid-lowering agent of the present invention has an excellent action of lowering a uric acid level, and the uric acid-lowering agent is useful in, for example, prevention or treatment of hyperuricemia, gout or the like.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: May 16, 2017
    Assignee: Suntory Holdings Limited
    Inventors: Toshihide Suzuki, Shinya Fukizawa, Yoshinori Beppu, Hiroshi Watanabe
  • Publication number: 20170129919
    Abstract: A cyclic dipeptide-containing composition containing each of tyrosine-containing cyclic dipeptides selected from the group consisting of cyclotryptophanyltyrosine, cycloseryltyrosine, cycloprolyltyrosine, cyclotyrosylglycine, cyclotyrosyltyrosine, cyclophenylalanyltyrosine, cycloleucyltyrosine, cyclolysyltyrosine, cyclohistidyltyrosine, cycloalanyltyrosine, cycloglutamyltyrosine, cyclovalyltyrosine, cycloisoleucyltyrosine, cyclothreonyltyrosine, cycloaspartyltyrosine, cycloasparaginyltyrosine, cycloglutaminyltyrosine, cycloarginyltyrosine, and cyclomethionyltyrosine, or a salt thereof in a specified amount. The cyclic dipeptide-containing composition of the present invention has an excellent action of lowering a uric acid level, and the cyclic dipeptide-containing composition is useful in, for example, prevention or treatment of hyperuricemia, gout or the like.
    Type: Application
    Filed: February 13, 2015
    Publication date: May 11, 2017
    Applicant: Suntory Holdings Limited
    Inventors: Toshihide Suzuki, Shinya Fukizawa, Yoshinori Beppu, Hiroshi Watanabe
  • Publication number: 20170123305
    Abstract: The present invention provides a mask blank including: a transparent substrate, a half-transparent layer for controlling a phase and a transmittance of the exposure light, formed on the transparent substrate, a middle layer formed on the half-transparent layer, and a light-shielding layer formed on the middle layer, wherein the light-shielding layer is constituted with a single metal material not including a transition metal; a film thickness of the light-shielding layer is 40 nm or less; and an optical density of a laminated body, in which three kinds of layers: the half-transparent layer, the middle layer, and the light-shielding layer are laminated, with respect to the exposure light is a value to the extent that the laminated body functions as a light-shielding region or more; the mask blank is used for producing a half tone type phase shift mask, and suitable for a lithography technique on a wafer from 40 nm half pitch and on for its high light-shielding property even thinning the light-shielding pattern
    Type: Application
    Filed: January 29, 2015
    Publication date: May 4, 2017
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Hiroshi WATANABE, Katsuya HAYANO, Hideyoshi TAKAMIZAWA, Youhei OHKAWA, Takashi ADACHI, Ayako TANI, Yoichi MIURA
  • Publication number: 20170120343
    Abstract: The cutting device includes a rotating portion for rotating the cutting tool in a rotation axis line of the cutting tool and a traveling means for making the cutting tool travel relative to a workpiece. The rotating means and the traveling means rotates the outer peripheral surface of the cutting tool and makes the cutting tool travel, having the outer peripheral surface function as the rake surface, so as to perform cutting machining.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 4, 2017
    Applicant: JTEKT CORPORATION
    Inventors: Takayuki AZUMA, Yoshihiko YAMADA, Kenji HAMADA, Masahiro KIJI, Hiroshi WATANABE
  • Publication number: 20170114030
    Abstract: Provided is a composition having an excellent physiological effect. Inventors have found that a composition in which the total amount of cyclic dipeptides including amino acids as constituent units, or salts thereof, is greater than or equal to a specific amount has the effect of improving sugar metabolism, and have also found that the sugar metabolism improvement effect is achieved by including given contents of specific cyclic dipeptides. This composition is advantageous in that it has an excellent sugar metabolism improvement effect, and that it can be taken in safely for a long period of time.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 27, 2017
    Applicant: SUNTORY HOLDINGS LIMITED
    Inventors: Toshihide Suzuki, Kenji Yamamoto, Yoshinori Beppu, Hiroshi Watanabe
  • Patent number: 9627706
    Abstract: A method is provided for manufacturing a fuel-cell stack that has a laminate including of a plurality of fuel cells that are laminated together. In each of these fuel cells, an MEA has an anode and a cathode joined respectively to the two sides of an electrolyte membrane is sandwiched between a pair of separators. The aforementioned method has the following steps: a sealing member layout step, in which fuel cells with sealing members applied at least between adjacent fuel cells are laminated together, forming a fuel cell module; and a pressure application step, in which pressure is applied to the fuel cell module in the lamination direction of the fuel cells, forming sealed regions from the sealing members. The lamination-direction thickness of the fuel cell module is controlled by controlling the amount of pressure applied to the fuel cell module in the pressure application step.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: April 18, 2017
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Keiji Ichihara, Akio Hoshina, Hiroshi Watanabe, Kazuhiro Kageyama
  • Patent number: 9623073
    Abstract: The present invention aims to provide antidepressants which are free from the problem of side effects and are excellent in safety. The present invention also aims to provide learning motivation improvers which are useful for improvement of learning motivation and can be ingested continuously. The present invention provides antidepressants and learning motivation improvers, each comprising a cyclic dipeptide with the 2,5-diketopiperazine structure as an active ingredient.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 18, 2017
    Assignees: SUNTORY HOLDINGS LIMITED, CEREBOS PACIFIC LIMITED
    Inventors: Nobuo Tsuruoka, Yoshinori Beppu, Hirofumi Kouda, Hiroshi Watanabe
  • Patent number: 9614029
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: April 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Patent number: 9614194
    Abstract: According to one embodiment, a battery includes an electrode group, at least one positive electrode current collector tab, at least one negative electrode current collector tab, and a case. The case includes a case portion and an edge portion. The edge portion includes a heat sealed part configured to seal the case portion and a non-sealed part. The electrode group is housed in the case portion while an end portion of at least one of the positive electrode current collector tab and the negative electrode current collector tab is provided in the non-sealed part.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Murata, Kengo Kurata, Akira Yajima, Hiroshi Watanabe
  • Publication number: 20170030251
    Abstract: A cooling device includes a first cooling medium circuit for circulating a cooling medium that passes through a main body of an engine to a first heat exchanger, a second cooling medium circuit for circulating a cooling medium that passes through the main body to a second heat exchanger, a control valve that is commonly used in the first and second cooling medium circuits, and a control device. The control valve includes a rotatable rotor, and is configured such that a rotation range of the rotor includes a water stop section in which the circuits are both closed. The control device restricts output power of the engine in a period in which the rotation angle is in the water stop section, when the rotor rotates via the water stop section at an operating time of the control valve.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 2, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroshi WATANABE
  • Patent number: 9560007
    Abstract: A server apparatus includes a storage unit to store table data including an IP address and a MAC address of each of information processing apparatuses connected to a network, the IP address and the MAC address being associated with each other in the table data; and a processor to transmit information having one of the IP addresses specified, and to update the table data based on information in a reply for the transmitted information, to determine whether the MAC address being associated with the IP address has been changed since a time-out possibly occurring while receiving or transmitting the information with the information processing apparatus, and to issue a command for freezing the corresponding IP address on use to an IP address assignment apparatus connected to the network if the MAC address has been changed.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 31, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Watanabe
  • Publication number: 20170024339
    Abstract: A technology precluding attacks through peripheral devices thefts to a network of electronic appliances, by utilizing physical chip identification devices, is disclosed. The electronic appliances in the network are divided into the peripheral devices and the stem servers managing the registration information of the peripheral devices. The stem servers are under the central control with software, and the peripheral devices are controlled at device-level with the physical chip identification devices implemented in the chip. Thus, the security of the whole network is efficiently enhanced.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 26, 2017
    Inventor: HIROSHI WATANABE
  • Publication number: 20170003487
    Abstract: A microscope system includes: a stage on which a specimen is placed; a light emitting LED configured to emit illumination light for illuminating the specimen; an optical system configured to condense the illumination light emitted by the light emitting LED and irradiate the specimen with the illumination light; an input unit configured to receive an input of a light control signal that adjusts a light amount of the light emitting LED; and a control unit configured to control, when the light control signal is input from the input unit, the light amount of the light emitting LED to become a light amount according to the light control signal by delaying the light control signal by a predetermined time from timing when the light control signal is input.
    Type: Application
    Filed: June 24, 2016
    Publication date: January 5, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Hideaki ENDO, Hiroshi WATANABE