Patents by Inventor Hiroshi Watanabe

Hiroshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180212049
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: March 21, 2018
    Publication date: July 26, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 10026644
    Abstract: Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate, wherein the first word lines and the second word lines are arranged periodically and extend in a first direction. Bit lines are formed over the first and second word lines, wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: July 17, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 10020367
    Abstract: An object of the present invention is to provide a silicon carbide semiconductor device with which the electric field at the time of switching is relaxed and the element withstand voltage can be enhanced. The distance between the outer peripheral end of a second surface electrode and the inner peripheral end of a field insulation film is smaller than the distance between an outer peripheral end of the second surface electrode and an inner peripheral end of the field insulation film in the case where the electric field strength applied to the outer peripheral lower end of the second surface electrode is calculated so as to become equal to the smallest dielectric breakdown strength among the dielectric breakdown strength of the field insulation film and the dielectric breakdown strength of the surface protective film at the time of switching when the value of dV/dt is greater than or equal to 10 kV/?s.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: July 10, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Akihiro Koyama, Hidenori Koketsu, Akemi Nagae, Kotaro Kawahara, Hiroshi Watanabe, Kensuke Taguchi, Shiro Hino
  • Publication number: 20180165045
    Abstract: According to one embodiment, an image forming apparatus includes a processor, a network interface and a display device. The network interface under processor control acquires identification information of a different image forming apparatus on which a user is determined to have use authority based on user identification information of the user. The network interface under processor control also acquires an image forming job registered with the different image forming apparatus based on the acquired identification information of the different image forming apparatus. The display device under processor control displays the image forming job acquired by the network interface.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: Takahiro HAGIWARA, Shinji MAKISHIMA, Koji ENDO, Hiroshi WATANABE, Akihiro MIZUTANI, Toshihiro IDA, Yusuke HAMADA, Kazuhiro OGURA, Takeo NISHIJIMA
  • Publication number: 20180149101
    Abstract: A shift control system which can reduce a shift shock is provided. A target torque determiner set a target torque of an engine based on an accelerator position. An actual torque determiner calculates an actual torque of the engine in the inertia phase. A controller calculates an integrated value of a difference between the target torque and the actual torque from a commencement of the inertia phase to a predetermined time point before a termination of the inertia phase, and corrects the target torque in a remaining period between the predetermined time point and the termination of the inertia phase.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 31, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi WATANABE, Akira EIRAKU
  • Publication number: 20180151070
    Abstract: Onboard terminal device includes its own vehicle information acquisition section, a vehicle-to-vehicle communication section, and a collision risk determination section. The vehicle information acquisition section acquires the vehicle information including position information of an own vehicle. The vehicle-to-vehicle communication section performs wireless communications with another vehicle to communicate one's vehicle information to another vehicle and to receive the another vehicle's information, which includes position information of the another vehicle, from the another vehicle. The collision risk determination section determines a risk of collision between the one vehicle and the another vehicle by using a predetermined determination algorithm.
    Type: Application
    Filed: June 13, 2016
    Publication date: May 31, 2018
    Inventors: Seiya KATOU, Hiroshi WATANABE, Takeshi ITO
  • Patent number: 9984736
    Abstract: According to an embodiment, a magnetic storage device includes a first, second, and third magnetoresistive effect elements, and a controller. The second and third magnetoresistive effect elements are in proximity to the first magnetoresistive effect element. When the controller receives an command which is associated with an operation of writing a first data item to the first magnetoresistive effect element, the controller is configured to perform a first operation of writing the first data item to the first magnetoresistive effect element, and a second operation of writing a second data item different from the first data item to the second magnetoresistive effect element and the third magnetoresistive effect element.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ahmetserdar Demiray, Masahiko Nakayama, Hiroshi Watanabe
  • Patent number: 9985093
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 29, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Patent number: 9985959
    Abstract: Technology prevents the peripheral devices from being taken over, to suppress the remote-attack on the network of electronic devices by applying the physical chip identification devices to the network. To realize this, a plurality of electronic appliances composing the network is divided into peripheral devices and stem servers that manage the registration information of the peripheral devices. The stem servers may be under the central control, whereas the peripheral devices hold the physical chip identification devices. By managing the peripheral devices in the level of a device like this, the security of the entire network is effectively improved.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: May 29, 2018
    Inventor: Hiroshi Watanabe
  • Publication number: 20180138272
    Abstract: Supposing x is defined as a position of an end of a depletion layer extending when a rated voltage V [V] is applied to a rear surface electrode, W1 is defined as a distance between the position x and an outer peripheral edge of a surface electrode in an outer peripheral direction, W2 is defined as a distance between the position x and an outer peripheral edge of a field insulating film in the outer peripheral direction, t [?m] is defined as a film thickness t [?m] of the field insulating film, a layout of a terminal part is defined so that an electrical field in the field insulating film at the position x expressed as W2V/t(W1+W2) is 3 MV/cm or smaller.
    Type: Application
    Filed: April 14, 2015
    Publication date: May 17, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei EBIHARA, Hiroshi WATANABE
  • Patent number: 9971238
    Abstract: The present invention provides a mask blank including: a transparent substrate, a half-transparent layer for controlling a phase and a transmittance of the exposure light, formed on the transparent substrate, a middle layer formed on the half-transparent layer, and a light-shielding layer formed on the middle layer, wherein the light-shielding layer is constituted with a single metal material not including a transition metal; a film thickness of the light-shielding layer is 40 nm or less; and an optical density of a laminated body, in which three kinds of layers: the half-transparent layer, the middle layer, and the light-shielding layer are laminated, with respect to the exposure light is a value to the extent that the laminated body functions as a light-shielding region or more; the mask blank is used for producing a half tone type phase shift mask, and suitable for a lithography technique on a wafer from 40 nm half pitch and on for its high light-shielding property even thinning the light-shielding pattern
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 15, 2018
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Hiroshi Watanabe, Katsuya Hayano, Hideyoshi Takamizawa, Youhei Ohkawa, Takashi Adachi, Ayako Tani, Yoichi Miura
  • Patent number: 9966467
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 8, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20180123119
    Abstract: According to an embodiment, a nonaqueous electrolyte battery including an electrode group and a nonaqueous electrolyte is provided. The electrode group is formed by winding a positive electrode, a negative electrode, and a separator arranged between the positive electrode and the negative electrode. The tension modulus of the separator in the winding direction is within a range of 200 (N/mm2) to 2,000 (N/mm2).
    Type: Application
    Filed: December 20, 2017
    Publication date: May 3, 2018
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Masataka SHIKOTA, Hidesato Saruwatari, Dai Yamamoto, Genki Yamagishi, Hiroshi Watanabe
  • Patent number: 9946279
    Abstract: An integrated circuit includes a voltage set input terminal, a current source, a voltage clipping circuit, and a voltage regulator. The clipping circuit receives a voltage from the terminal and supplies a voltage onto a reference voltage input of the regulator. The magnitude of an output voltage VOUT output by the regulator is the voltage on reference voltage input multiplied by the voltage gain of the regulator. The user sets VOUT by attaching an external resistor to the terminal. Current from the current source flows out of the terminal, and through the external resistor, thereby setting the voltage on the terminal. If the voltage on the terminal is between V1 and V2, then VOUT is a fixed multiple of the voltage. If the voltage is less than V1, then VOUT is a predetermined VOUTMIN value. If the voltage is greater than V2, then VOUT is a predetermined VOUTMAX value.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: April 17, 2018
    Assignee: Active-Semi, Inc.
    Inventors: Khanh Q. Dinh, Tung V. Nguyen, Hiroshi Watanabe
  • Publication number: 20180076957
    Abstract: A network includes a logical network and a physical network. The logical network includes a plurality of logical nodes. Each logical node is connected to a respective identification core. Each identification core includes at least one semiconductor chip having a physical randomness. Each semiconductor chip generates one of a plurality of pairs of private keys and public keys based on the physical randomness thereof according to an input received by the one of the at least one semiconductor chip under a public key cryptography. One of the public keys is regarded as a logical address of one of the logical nodes, which is connected to one of the identification cores. The physical network includes a plurality of physical nodes. Each identification core is one of components in each physical node. The logical network is uniquely linked to the physical network by the pairs of private keys and public keys.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 15, 2018
    Inventor: Hiroshi Watanabe
  • Publication number: 20180063360
    Abstract: An image processing apparatus includes a scanner, a communication interface, and a controller. The controller is configured to generate property and setting data of image data that is generated based on image scanning by the scanner, and control the communication interface to transmit the image data and the property and setting data thereof to a server connected to the image processing apparatus through a network, so that the image data and the property and setting data thereof are stored therein in association with each other.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Toshihiro IDA, Hiroshi WATANABE, Kazuhiro OGURA, Takahiro HAGIWARA, Shinji MAKISHIMA, Akihiro MIZUTANI, Yusuke HAMADA, Ken SAKUTA
  • Publication number: 20180063489
    Abstract: A projection display device includes: a light source device which emits source light; a first polarizer passes the source light in a first polarization state; a reflective liquid crystal panel; an illumination optical system which causes the source light to be incident to the reflective liquid crystal panel; a second polarizer passes the source light in the first polarization state from the first polarizer, and reflects the source light in a second polarization state from the reflective liquid crystal panel; a projection optical system which projects the source light reflected by the second polarizer; a support member which includes an outer member that supports the first polarizer and the reflective liquid crystal panel and an inner member that is fixed to the outer member in an internal space of the outer member and supports the second polarizer; and a seal mechanism which seals the internal space.
    Type: Application
    Filed: July 27, 2017
    Publication date: March 1, 2018
    Inventors: Takatsugu Aizaki, Hiroshi Watanabe
  • Patent number: 9903259
    Abstract: A change in a valve opening degree from an opening degree (a) to an opening degree (d) is caused by a decrease in a radiator outlet water temperature, and at such time a flow rate through a radiator enters a boiling region. Therefore, when such entry is predicted, a target engine outlet water temperature is forcedly changed from 105° C. to 100° C. Thereupon, the valve opening degree is changed from the opening degree (a) to an opening degree (f). The flow rate through the radiator when the valve opening degree is the opening degree (f) is greater than the flow rate through the radiator when the valve opening degree is the opening degree (d), and furthermore, the flow rate through the radiator does not enter the boiling region while the valve opening degree is changing from the opening degree (a) to the opening degree (f).
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: February 27, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Watanabe, Ryo Michikawauchi
  • Publication number: 20180052077
    Abstract: An object is to carry out an abnormality diagnosis for a variable compression ratio mechanism without adding any special hardware configuration for estimating a compression ratio. An abnormality diagnostic device for a variable compression ratio mechanism adapted to be applied to an internal combustion engine comprises a controller configured to calculate a predetermined rotational speed difference which is a rotational speed difference, between an engine rotational speed at a predetermined crank angle before or after compression top dead center and an engine rotational speed in the vicinity of the compression top dead center for a predetermined cylinder at the time of carrying out fuel cut processing, set a reference range of the predetermined rotational speed difference, and make a diagnosis that abnormality has occurred in the variable compression ratio mechanism when the predetermined rotational speed difference is out of the reference range.
    Type: Application
    Filed: August 14, 2017
    Publication date: February 22, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Noriyasu ADACHI, Tomoya OTA, Hiroshi WATANABE, Yoshio UENO, Takayoshi KAWAI, Aya YAMADA
  • Publication number: 20180053542
    Abstract: According to an embodiment, a magnetic storage device includes a first, second, and third magnetoresistive effect elements, and a controller. The second and third magnetoresistive effect elements are in proximity to the first magnetoresistive effect element. When the controller receives an command which is associated with an operation of writing a first data item to the first magnetoresistive effect element, the controller is configured to perform a first operation of writing the first data item to the first magnetoresistive effect element, and a second operation of writing a second data item different from the first data item to the second magnetoresistive effect element and the third magnetoresistive effect element.
    Type: Application
    Filed: February 6, 2017
    Publication date: February 22, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Ahmetserdar DEMIRAY, Masahiko NAKAYAMA, Hiroshi WATANABE