Patents by Inventor Hiroshi Yuzurihara

Hiroshi Yuzurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5527730
    Abstract: An insulating film is formed on the surface of the base of a semiconductor, and a portion of the insulating film is removed to cause the surface to appear outside. The exposed surface is terminated with hydrogen, and then energy beams are applied to selectively remove the terminating hydrogen. Metal is selectively deposited on the portion terminated with left hydrogen atoms.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: June 18, 1996
    Assignee: Conon Kabushiki Kaisha
    Inventors: Yuzo Kayaoka, Tetsuo Asaba, Kenji Makino, Hiroshi Yuzurihara, Kei Fujita, Seiji Kamei, Yutaka Akino, Yutaka Yuge, Mineo Shimotsusa, Hideshi Kuwabara
  • Patent number: 5482893
    Abstract: An alignment method for a semiconductor device having a conductive thin film on a conductive substrate surface across an insulation film, comprises steps of:a) forming in the insulation film, at least two apertures exposing the substrate surface therein;b) selectively depositing a conductive material in the apertures thereby forming a stepped portion in at least one of said apertures; andc) forming the conductive thin film at least on said insulation film. The alignment is conducted utilizing the stepped portion.
    Type: Grant
    Filed: January 19, 1994
    Date of Patent: January 9, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiko Okabe, Genzo Monma, Hiroshi Yuzurihara
  • Patent number: 5428237
    Abstract: An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with the channel region, the semiconductor region having the same conductivity type as that of the channel region and a higher impurity concentration than the channel region. The gate electrode has at least two opposing portions. The plurality of major electrode regions are provided on an substrate insulating film. The transistor is activated in a state where the semiconductor region is maintained at a predetermined voltage. A semiconductor device includes a plurality of memory cells, each of which includes the aforementioned insulated gate type transistor and an electrically breakable memory element provided on one of the major electrode regions.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: June 27, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Mamoru Miyawaki, Akira Ishizaki, Genzo Momma, Tetsunobu Kochi
  • Patent number: 5331197
    Abstract: A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: July 19, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mamoru Miyawaki, Akira Ishizaki, Genzo Momma, Hiroshi Yuzurihara, Tetsunobu Kohchi
  • Patent number: 5218232
    Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least the layers of mutually different conductive types, comprises a first portion principally composed of the same component as the principal component of the semiconductor layers, and a second portion consisting of a metal.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: June 8, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Shunsuke Inoue, Mamoru Miyawaki, Shigeyuki Matsumoto
  • Patent number: 5192680
    Abstract: A method for producing a semiconductor device containing steps of forming a stepped pattern on the surface of a semiconductor substrate and forming a gaseous grown crystal layer thereon, which comprises positioning an alignment pattern (for example 6c) included in the first-mentioned pattern diagonally with respect to an in-plane direction of faster pattern growth in said gaseous crystal growth.
    Type: Grant
    Filed: June 2, 1989
    Date of Patent: March 9, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Naruse, Genzo Momma, Hiroshi Yuzurihara