Patents by Inventor Hiroto Nakai
Hiroto Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150071156Abstract: According to the embodiments, when a communication apparatus is a publisher, a transmission message including a first identifier is transmitted using first transmission power, when the communication apparatus is a subscriber, data of a reception message including the first identifier is stored in a nonvolatile memory, when at least a part of the reception message cannot be received, a repair message for requesting retransmission of the reception message is transmitted from a wireless interface unit using second transmission power, and when there is no response, a repair message is transmitted using third transmission power that is larger than the second transmission power.Type: ApplicationFiled: March 13, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi MAEDA, Arata Miyamoto, Masahiro Ishiyama, Hiroto Nakai
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Publication number: 20150058588Abstract: According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.Type: ApplicationFiled: October 8, 2014Publication date: February 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroto NAKAI, Kenichi MAEDA, Tatsunori KANAI
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Patent number: 8892810Abstract: According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.Type: GrantFiled: February 17, 2012Date of Patent: November 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Tatsunori Kanai, Kenichi Maeda
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Patent number: 8738851Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.Type: GrantFiled: May 9, 2013Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
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Patent number: 8589639Abstract: According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory.Type: GrantFiled: September 17, 2010Date of Patent: November 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Tatsunori Kanai
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Publication number: 20130254471Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.Type: ApplicationFiled: May 9, 2013Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
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Publication number: 20130198437Abstract: In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information.Type: ApplicationFiled: July 27, 2012Publication date: August 1, 2013Inventors: Takashi OMIZO, Tsutomu OWA, Atsushi KUNIMATSU, Hiroto NAKAI, Masaki MIYAGAWA, Reina NISHINO, Hiroyuki SAKAMOTO
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Publication number: 20130163755Abstract: A digital content protection method includes distributing, together with an encrypted content, an encrypted protected program key, a protected content key, and a protected code including an individual instruction code, at least some elements of which are designed according to a unique operation code specification for each content player or for each content player group.Type: ApplicationFiled: May 30, 2011Publication date: June 27, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuji Nagai, Hiroyuki Sakamoto, Hiroto Nakai, Seiji Miyata, Hideki Mimura
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Patent number: 8458436Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.Type: GrantFiled: January 30, 2012Date of Patent: June 4, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
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Patent number: 8400816Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.Type: GrantFiled: September 20, 2011Date of Patent: March 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Hirofumi Inoue, Hiroto Nakai
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Publication number: 20120246397Abstract: According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.Type: ApplicationFiled: June 8, 2012Publication date: September 27, 2012Inventors: Hiroto NAKAI, Tatsunori Kanai
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Publication number: 20120216003Abstract: According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.Type: ApplicationFiled: February 17, 2012Publication date: August 23, 2012Inventors: Hiroto NAKAI, Tatsunori Kanai, Kenichi Maeda
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Publication number: 20120191900Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.Type: ApplicationFiled: January 17, 2012Publication date: July 26, 2012Inventors: Atsushi KUNIMATSU, Masaki MIYAGAWA, Hiroshi NOZUE, Kazuhiro KAWAGOME, Hiroto NAKAI, Hiroyuki SAKAMOTO, Tsutomu OWA, Tsutomu UNESAKI, Reina NISHINO, Kenichi MAEDA, Mari TAKADA
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Patent number: 8184470Abstract: A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.Type: GrantFiled: June 25, 2008Date of Patent: May 22, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Hiroto Nakai
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Publication number: 20120124290Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.Type: ApplicationFiled: January 30, 2012Publication date: May 17, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
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Patent number: 8135900Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.Type: GrantFiled: September 24, 2008Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
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Publication number: 20120008372Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Haruki Toda, Hirofumi Inoue, Hiroto Nakai
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Patent number: 8031508Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.Type: GrantFiled: November 7, 2008Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Hirofumi Inoue, Hiroto Nakai
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Publication number: 20110131366Abstract: According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory.Type: ApplicationFiled: September 17, 2010Publication date: June 2, 2011Inventors: Hiroto NAKAI, Tatsunori Kanai
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Publication number: 20100211725Abstract: An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.Type: ApplicationFiled: October 17, 2008Publication date: August 19, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Nagashima, Hiroto Nakai