Abstract: There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

Abstract: In the semiconductor integrated circuit, the data delay circuit and data latch circuit are connected between the sense amplifier circuit and the output buffer circuit. A pulse signal for controlling the output buffer is first generated according to a pulse output signal of the address change detection circuit, and then a latch signal which permits output data of the data detection circuit obtained before the change of the address input signal to be latched by the data latch circuit for a preset period of time is generated. Next, a delay signal is generated which sets the delay time of the data delay circuit to be short in a case where data detected by the data detection circuit is not output from the output buffer circuit, and sets the delay time of the data delay circuit to be long in a case where data is output from the output buffer circuit. Generation of the delay signal is interrupted after the pulse signal of the address change detection circuit is interrupted.

Abstract: The invention involves a semiconductor memory device having a memory cell with a drain, a gate and a source. The gate of the memory cell is supplied with a first potential for reading a memory cell data. A first reference line is connected to the drain of a first reference cell to receive a first reference cell data. A second reference cell has a drain, a gate and a source. A second reference line is connected to the drain of the second reference cell for receiving a second reference cell data. A gate voltage generating circuit having an output node is connected to the gate of the first reference cell for controlling the gate potential of the first reference cell so that the potentials at the first and second reference lines have the same power source voltage dependancy. A data detecting circuit reads the memory cell data in accordance with the comparison result between the potentials.

Abstract: In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: There is disclosed a semiconductor integrated circuit provided with an input circuit including an N-channel MOS transistor of which threshold voltage is set to a value lower than those of N-channel MOS transistors constituting other internal circuits of the integrated circuit. Thus, a circuit having a high operating margin for power supply noises is provided. This circuit further comprises a P-channel MOS transistor constituting a portion of a NOR gate or a NAND gate together with the above-mentioned N-channel MOS transistor.

Abstract: A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.

Abstract: In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: An output buffer produces an output data at an output terminal. A first MOS transistor charges the output terminal toward a first supply potential when turned on. The source and drain of the first MOS transistor are connected between the output terminal and a first supply potential terminal. A second MOS transistor discharges the output terminal toward a second supply potential when turned on. The source and drain of the second MOS transistor are connected between the output terminal and a second supply potential terminal. A resistive element charges the gate of the second MOS transistor toward the first supply potential when turned on. The resistive element is connected between the first supply potential terminal and the gate of the second MOS transistor. The resistance value of the resistive element has nearly a constant value.

Abstract: A voltage detecting circuit comprising a voltage-input terminal for receiving a first voltage or a second voltage higher than the first voltage, switch means connected between the voltage-input terminal and a first node, and an inverter circuit having an input terminal coupled to the first node and an output terminal coupled to a second node. The switch circuit is turned on when the voltage at the voltage-input terminal is higher than a predetermined value which is between the higher than the first voltage and lower than the second voltage, and is turned off when the voltage at the voltage-input terminal is lower than the predetermined value.

Abstract: A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor.