Abstract: A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.

Abstract: To provide a finger vein vein pattern input apparatus to be felt that one finger is put surely at a predetermined position during an authentication time, thereby a good convenience is attained. A finger vein pattern input apparatus for a personal authentication is constituted having a main body, a finger put stand installed on the main body, an irradiation means installed in an interior portion of the main body and for light irradiating a finger put on the finger put stand, and an imaging means for taking an image the light irradiated finger through an imaging window formed the finger put stand. To the finger put stand, an irradiation window arranged on a penetrated hole provided on the finger put stand and for passing through a light from the irradiation means is provided, and a hand touch feeling section having a smooth surface of a hand touch by approaching the imaging window and the irradiation window and by distinguishing from a peripheral rough surface having grains.

Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: A semiconductor integrated circuit device includes a global-bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which selects one of the first and the second transistors, and a data latch circuit. The data latch circuit includes a data amplifier circuit which amplifies readout data from the first and the second section bit lines, a first data holding circuit which holds readout data and programming data to the first section bit line, and a second data holding circuit which holds readout data and programming data to the second section bit line.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A semiconductor integrated circuit device includes a global-bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which selects one of the first and the second transistors, and a data latch circuit. The data latch circuit includes a data amplifier circuit which amplifies readout data from the first and the second section bit lines, a first data holding circuit which holds readout data and programming data to the first section bit line, and a second data holding circuit which holds readout data and programming data to the second section bit line.

Abstract: A semiconductor integrated circuit device includes a global bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which selects one of the first and the second transistors, and a data latch circuit. The data latch circuit includes a data amplifier circuit which amplifies readout data from the first and the second section bit lines, a first data holding circuit which holds readout data and programming data to the first section bit line, and a second data holding circuit which holds readout data and programming data to the second section bit line.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A semiconductor integrated circuit device includes a global bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which selects one of the first and the second transistors, and a data latch circuit. The data latch circuit includes a data amplifier circuit which amplifies readout data from the first and the second section bit lines, a first data holding circuit which holds readout data and programming data to the first section bit line, and a second data holding circuit which holds readout data and programming data to the second section bit line.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A pixel unit 1 comprises a nonvolatile memory transistor MT, which is formed on a p-type well 12 of a semiconductor substrate 10 and which has a floating gate 14 and a control gate 16, and selecting gate transistors ST1 and ST2 which share a diffusion layer 17 with the memory transistor MT and which is formed on both sides of the memory transistor MT. The memory transistor MT has a photoelectric converting region PD in the substrate directly below the floating gate 14. By irradiating the memory transistor MT with light while a positive writing voltage is applied to the control gate 16, charges generated in the photoelectric converting region PD are injected into the floating gate 14 to be held therein, so that pixel information is stored as a threshold voltage.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.

Abstract: Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.

Abstract: A nonvolatile semiconductor memory device has a defective block detecting circuit 10 for detecting and temporarily storing a block including a defective memory cell, by detecting the potentials of a memory cell array 1, a row decoder 2, a column decoder 4, a sense amplifier circuit 3, a driving voltage generating circuit 9 for generating a driving voltage boosted in accordance with writing and erasing of data, and a signal line driven by the driving voltage generated by the driving voltage generating circuit 9. The defective block detecting circuit 10 is activated at the beginning of a test control sequence when a batch writing test is carried out every a batch erasing or writing operation every an erasing unit of the memory cell array 1, and a control circuit 7 controls the stop of the supply of the driving voltage to the defective memory cell in the test sequence on the basis of the detected output of the defective block detecting output 10.