Patents by Inventor Hiroyuki Fujimoto

Hiroyuki Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8819509
    Abstract: An integrated circuit includes a storing unit; and a tester that executes a write and read test on the storing unit based on received test information including a pair of address and data, the tester including: a first retain unit that retains, when a write is made based on the test information, the first write address and the first write data used in the write; a first generator that generates, based on the first write address retained in the first retain unit, a first read address used for reading first read data from the first read address in the storing unit simultaneously with writing second write data to a second write address based on the test information; and a second generator that generates, based on the first write data retained in the first retain unit, an expected value of the first read data.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahiro Yanagida, Hiroyuki Fujimoto
  • Patent number: 8725376
    Abstract: A vehicle can be operated in a first drive mode in which a front differential is set to a non-driven state and a rear differential is set to a differential state, a second drive mode in which the front differential is set to a non-driven state and the rear differential is set to a differential locked state, a third drive mode in which the front differential is set to a differential state and the rear differential is set to a differential locked state, and a fourth drive mode in which the front differential is set to a differential locked state and the rear differential is set to a differential locked state. Transition is allowed only between adjacent drive modes.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: May 13, 2014
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Naoki Murota, Hiroyuki Fujimoto, Hiroshi Kawamura
  • Publication number: 20140093767
    Abstract: To realize high capacity of batteries, an object of the invention is to provide nonaqueous electrolyte secondary batteries which are unlikely to become swollen when charged to a high voltage and allowed to stand in a high temperature atmosphere. The nonaqueous electrolyte secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, a nonaqueous electrolyte, and a separator disposed between the positive electrode and the negative electrode. An inorganic particle layer is disposed between the positive electrode and the separator or between the negative electrode and the separator. The inorganic particle layer contains a polymer with a polyethylene glycol group. The polymer with a polyethylene glycol group has an average molecular weight of not less than 200.
    Type: Application
    Filed: May 10, 2012
    Publication date: April 3, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Nobuhiro Sakitani, Takanobu Chiga, Hiroyuki Fujimoto
  • Publication number: 20130330628
    Abstract: The present invention provides a positive electrode active material for a nonaqueous electrolyte secondary battery which is capable of improving an initial discharge capacity and suppressing a decrease in discharge voltage and a decrease in battery capacity even in repeated charge-discharge cycles, a positive electrode using the active material, and a nonaqueous electrolyte secondary battery using the positive electrode. The positive electrode active material includes a particle 21 of a lithium transition metal composite oxide containing lithium, nickel, and manganese and having a layered structure; and a particle 22 of a compound of at least one element adhered to a portion of the surface of the particle 21 and selected from the rare earth elements with atomic numbers 59 to 71.
    Type: Application
    Filed: January 23, 2012
    Publication date: December 12, 2013
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazuhiro Hasegawa, Takeshi Ogasawara, Daizo Jito, Shun Nomura, Hiroyuki Fujimoto
  • Patent number: 8597834
    Abstract: A nonaqueous electrolyte secondary battery including a negative electrode containing a graphite material as the negative active material, a positive electrode containing lithium cobalt oxide as a main component of the positive active material and a nonaqueous electrolyte solution, the battery being characterized in that the lithium cobalt oxide contains a group IVA element selected from the group consisting of Ti, Zr and Hf and a group IIA element of the periodic table, the nonaqueous electrolyte solution contains 0.2-1.5% by weight of a sulfonyl-containing compound and preferably further contains 0.5-4% by weight of vinylene carbonate.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: December 3, 2013
    Assignees: Ube Industries Ltd., Sanyo Electric Co., Ltd.
    Inventors: Koji Abe, Kazuhiro Miyoshi, Yasufumi Takahashi, Hiroyuki Fujimoto, Akira Kinoshita, Shingo Tode, Ikuro Nakane, Shin Fujitani
  • Publication number: 20130316227
    Abstract: The present invention is to provide a non-aqueous electrolyte secondary battery that can suppress a decrease in discharge performance and a decrease in residual capacity after storage at charged state under high temperature. The non-aqueous electrolyte secondary battery includes a positive electrode containing a positive electrode active material, a negative electrode containing a negative electrode active material, a non-aqueous electrolyte, and a separator provided between the positive electrode and the negative electrode, the positive electrode active material includes lithium cobaltate and an erbium compound 22 fixed to at least part of the surface of this lithium cobaltate 21, and the non-aqueous electrolyte contains 1,3-bis(isocyanatomethyl)cyclohexane.
    Type: Application
    Filed: February 27, 2012
    Publication date: November 28, 2013
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shun Nomura, Kazuhiro Hasegawa, Takeshi Ogasawara, Hiroyuki Fujimoto
  • Publication number: 20130288399
    Abstract: An energy beam processing apparatus cutting an interconnection by irradiating the interconnection with an energy beam while scanning, the energy beam processing apparatus including an irradiation unit which irradiates the interconnection with the energy beam while scanning; a measurement unit which measures a resistance value of the interconnection; and a control unit which controls a scan and an irradiation of the energy beam by the irradiation unit, the control unit controlling at least one of a scan rate and an irradiation intensity of the energy beam in accordance with a resistance value measured by the measurement unit, and controlling the irradiation unit to stop the irradiation of the energy beam when the resistance value measured by the measurement unit exceeds a prescribed value.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Hiroyuki FUJIMOTO
  • Publication number: 20130245995
    Abstract: A cutting distance calculating device for a multi-axis working machine acquires axis positions at calculation times for at least three linear axes and two rotation axes of a multi-axis working machine and calculates the position of a tool tip point on the basis of the acquired axis positions. This device accumulates moving distances (cutting distances) of the tool tip points from the calculated position of the tool tip point to thereby calculate a cutting distance and predicts tool wear and tool life on the basis of the calculated cutting distance.
    Type: Application
    Filed: January 18, 2013
    Publication date: September 19, 2013
    Applicant: FANUC CORPORATION
    Inventors: Toshiaki OTSUKI, Hiroyuki FUJIMOTO
  • Publication number: 20130241009
    Abstract: A memory cell region comprises a first interlayer insulating film having a bit contact hole, a contact plug formed of a first conductor film embedded in the bit contact hole, and a second conductor film which is stacked on the first interlayer insulating film to constitute a bit line connected to the contact plug. A peripheral transistor region comprises a peripheral transistor having a gate insulating film and a gate electrode stack formed on the gate insulating film. The gate electrode stack is provided with a metal gate film formed on the gate insulating film, an upper gate film stacked on the metal gate film, and a third conductor film stacked on the upper gate film. A height from a semiconductor substrate to a top face of the upper gate film is equal to or lower than a height of a top face of the first interlayer insulating film.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 19, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiroyuki FUJIMOTO
  • Patent number: 8492814
    Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: July 23, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Shinpei Iijima
  • Patent number: 8459395
    Abstract: A switching device of a driving power transmission system equipped in an off-road vehicle, including a switching lever configured to switch driving power transmission of the driving power transmission system, and a negative-pressure actuator module that is coupled to the switching lever and is configured to operate the switching lever.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: June 11, 2013
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Haruo Kitai, Hiroyuki Fujimoto
  • Patent number: 8436409
    Abstract: In a semiconductor device of the invention, a semiconductor pillar configuring a vertical MOS transistor has an upper pillar having a first width and a lower pillar having a second width. A side surface of the upper pillar is covered with a second insulation film and a third insulation film and the lower pillar is covered with a first insulation film, which is a gate insulation film, from a side surface thereof to the second insulation film. A gate electrode is insulated from an upper conductive layer by the second and third insulation films.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 7, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Publication number: 20130111281
    Abstract: An integrated circuit includes a storing unit; and a tester that executes a write and read test on the storing unit based on received test information including a pair of address and data, the tester including: a first retain unit that retains, when a write is made based on the test information, the first write address and the first write data used in the write; a first generator that generates, based on the first write address retained in the first retain unit, a first read address used for reading first read data from the first read address in the storing unit simultaneously with writing second write data to a second write address based on the test information; and a second generator that generates, based on the first write data retained in the first retain unit, an expected value of the first read data.
    Type: Application
    Filed: August 31, 2012
    Publication date: May 2, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Yanagida, Hiroyuki Fujimoto
  • Patent number: 8409955
    Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A gate insulating film is formed on an inside wall of the groove. A buried gate electrode is formed on the gate insulating film and on a bottom portion of the groove. A cap insulating film covering the buried gate electrode is formed in an upper portion of the groove. The cap insulating film has a top surface which is different in level from a top surface of the semiconductor substrate. A first inter-layer insulating film is formed on the top surface of the semiconductor substrate and on the top surface of the cap insulating film. The first inter-layer insulating film with a flat top surface fills a gap in level between the top surface of the semiconductor substrate and the top surface of the cap insulating film.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: April 2, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 8399131
    Abstract: Disclosed is a composite negative electrode active material including a graphitizable carbon material containing a layered structure formed of stacked carbon layers partially having a three-dimensional regularity, and a low crystalline carbon material. A negative electrode including the composite negative electrode active material is used to produce a non-aqueous electrolyte secondary battery. The non-aqueous electrolyte secondary battery thus produced has a high energy density and demonstrates a high output/input performance for a long period of time in various environments of high to low temperatures.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: March 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Ozaki, Hiroyuki Fujimoto
  • Patent number: 8343662
    Abstract: A nonaqueous electrolyte secondary battery in which a lithium transition metal complex oxide containing at least Ni and Mn as transition metals and having a layered structure is used as a positive active material, the lithium transition metal complex oxide containing at least Ni and Mn as transition metals and having a layered structure further containing zirconium.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: January 1, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shingo Tode, Akira Kinoshita, Hiroyuki Fujimoto, Yasufumi Takahashi, Ikuro Nakane, Shin Fujitani
  • Publication number: 20120313156
    Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.
    Type: Application
    Filed: August 23, 2012
    Publication date: December 13, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroyuki FUJIMOTO, Shinpei IIJIMA
  • Patent number: 8310002
    Abstract: A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film covers a side surface of the pillar. The gate electrode is separated from the pillar by the gate insulating film. The second diffusion region is disposed in an upper portion of the pillar. The contact plug is connected to the second diffusion region. The contact plug is connected to the entirety of the top surface of the pillar.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 8294205
    Abstract: A semiconductor device includes a first semiconductor pillar, a first insulating film covering a side face of the first semiconductor pillar, a first electrode covering the first insulating film, a second semiconductor pillar, a second insulating film covering a side face of the second semiconductor pillar, and a second electrode covering the second insulating film. The top level of the second electrode is higher than the top level of the first electrode.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: October 23, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 8278172
    Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: October 2, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Shinpei Iijima