Patents by Inventor Hiroyuki Fujimoto

Hiroyuki Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110177391
    Abstract: A non-aqueous electrolyte secondary battery using lithium-containing transition metal composite oxide which has a layer structure, contains a lot of Ni and Mn and is inexpensive as a positive electrode active material and attaining high output characteristics even under low temperature environment is provided. The non-aqueous electrolyte secondary battery includes a positive electrode 11 containing a positive electrode active material, a negative electrode 12 containing a negative electrode active material and a non-aqueous electrolyte 14 having lithium ion conductivity, wherein lithium-containing transition metal composite oxide having a layer structure and being represented by a general formula Li1+xNiaMnbCocO2+d wherein x, a, b, c and d satisfy x+a+b+c=1, 0.25?a?0.60, 0.25?b?0.60, 0?c?0.40, 0?x?0.10, 0.7?a/b?2.0 and ?0.1?d?0.
    Type: Application
    Filed: September 17, 2009
    Publication date: July 21, 2011
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazunari Ookita, Fumiharu Niina, Hiroyuki Fujimoto, Chihiro Yada
  • Publication number: 20110143509
    Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A gate insulating film is formed on an inside wall of the groove. A buried gate electrode is formed on the gate insulating film and on a bottom portion of the groove. A cap insulating film covering the buried gate electrode is formed in an upper portion of the groove. The cap insulating film has a top surface which is different in level from a top surface of the semiconductor substrate. A first inter-layer insulating film is formed on the top surface of the semiconductor substrate and on the top surface of the cap insulating film. The first inter-layer insulating film with a flat top surface fills a gap in level between the top surface of the semiconductor substrate and the top surface of the cap insulating film.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiroyuki FUJIMOTO
  • Patent number: 7947550
    Abstract: A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: May 24, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yoshihiro Takaishi
  • Publication number: 20110094813
    Abstract: In an all terrain vehicle, an engine unit is at least partially disposed under a seat. An exhaust pipe includes a first portion, a second portion and a third portion. The first portion is connected to a rear surface of the engine unit, and extends rearward therefrom. The second portion is connected to the first portion, and has a U-shaped configuration. The third portion is connected to the second portion, and extends forward therefrom. A muffler is connected to the exhaust pipe. The muffler is arranged such that the first portion and the third portion at least partially overlap with an area located between two tangent lines of the muffler. The tangent lines of the muffler are perpendicular or substantially perpendicular to a tangent line shared by the first portion and the third portion.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 28, 2011
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Yasuhiro SUZUKI, Hiroyuki FUJIMOTO, Hikaru MORIYA, Satoshi KUBOTA
  • Publication number: 20110094818
    Abstract: In an all terrain vehicle, an engine body of an engine unit is positioned along a center line that is perpendicular or substantially perpendicular to a transverse direction of the vehicle. A continuously variable transmission of the engine unit is disposed transversely lateral to the engine body. A center console includes an inner space. The center console is disposed in a transverse center portion of a cabin space. The center console connects a space positioned forward of a front panel and a space positioned under a seat. An intake duct is connected to an upper surface of the engine unit, and extends forward therefrom. The intake duct is at least partially disposed in the interior of the center console. An exhaust duct is connected to the engine unit, and extends rearward therefrom.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 28, 2011
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Yasuhiro SUZUKI, Takehiko ARAI, Hiroyuki FUJIMOTO, Yasuhiro OISHI
  • Patent number: 7928506
    Abstract: The semiconductor device comprises a word line and a bit line. The word line comprises a gate electrode and a first metal interconnect. The first metal interconnect has contact with the gate electrode and extends into a region upper than a first impurity-diffused region in a first direction. The bit line comprises a connecting part and a second metal interconnect. The connecting part is formed so as to have contact with at least part of the side surface of the first impurity-diffused region. The second metal interconnect has contact with the connecting part and extends into a region lower than the semiconductor region in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: April 19, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 7924022
    Abstract: An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: April 12, 2011
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Fujimoto
  • Patent number: 7888737
    Abstract: A semiconductor device includes: a monocrystalline substrate; an inter-layer film formed on the monocrystalline substrate; a contact hole penetrating the inter-layer film and partially exposing an upper surface of the monocrystalline substrate; a sidewall formed on an inner surface of the contact hole; a plurality of first monocrystalline layers which include few defects, fill the contact hole, and cover the inter-layer film; and a plurality of second monocrystalline layers which include many defects and cover the sidewall and an upper surface of the inter-layer film so as to be sandwiched between the first monocrystalline layers and the inter-layer film.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 15, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yuki Togashi
  • Publication number: 20110033994
    Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroyuki FUJIMOTO, Shinpei IIJIMA
  • Publication number: 20100330774
    Abstract: A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 30, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroyuki FUJIMOTO, Yoshihiro TAKAISHI
  • Patent number: 7858508
    Abstract: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of the trench and a surface of the semiconductor substrate. A conductive film is formed to fill the trench whose surface is covered with the an insulating film. Source/drain regions are formed on both sides of the trench.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: December 28, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda, Fumiki Aiso, Yuki Koga
  • Patent number: 7858237
    Abstract: A nonaqueous electrolyte secondary battery includes a positive electrode containing a positive active material, a negative electrode containing a negative active material and a nonaqueous electrolyte. Characteristically, the positive active material comprises a mixture of a lithium transition metal complex oxide A obtained by incorporating at least Zr and Mg into LiCoO2 and a lithium transition metal complex oxide B having a layered structure and containing at least Ni and Mn as the transition metal.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: December 28, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasufumi Takahashi, Akira Kinoshita, Shingo Tode, Kazuhiro Hasegawa, Hiroyuki Fujimoto, Ikuro Nakane, Shin Fujitani
  • Patent number: 7833867
    Abstract: A sacrifice oxide film is formed in a Fin semiconductor substrate portion, and impurities are then implanted in the semiconductor substrate through a mask pattern as a mask. Thereafter, the sacrifice oxide film is removed to expose the semiconductor substrate. A gate insulating film is then formed on the exposed semiconductor substrate.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: November 16, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 7829418
    Abstract: A semiconductor apparatus including a trench gate transistor having at least an active region surrounded by a device isolation insulating film; a trench provided by bringing both ends thereof into contact with the device isolation insulating film in the active region; a gate electrode formed in the trench via a gate insulating film; and a diffusion layer formed close to the trench; on a semiconductor substrate, and also includes an opening portion positioned on one surface of the semiconductor substrate; a pair of first inner walls positioned in a side of the device isolation insulating film and connected with the opening portion; a pair of second inner walls positioned in a side of the active region and connected with the opening portion; and a bottom portion positioned opposite to the opening portion and connected with the first inner walls and the second inner walls, wherein a cross sectional outline of the second inner wall is substantially linear, and a burr generated inside the trench is removed or redu
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: November 9, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Yasuhiko Ueda, Hiroyuki Fujimoto
  • Publication number: 20100262347
    Abstract: A vehicle can be operated in a first drive mode in which a front differential is set to a non-driven state and a rear differential is set to a differential state, a second drive mode in which the front differential is set to a non-driven state and the rear differential is set to a differential locked state, a third drive mode in which the front differential is set to a differential state and the rear differential is set to a differential locked state, and a fourth drive mode in which the front differential is set to a differential locked state and the rear differential is set to a differential locked state. Transition is allowed only between adjacent drive modes.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 14, 2010
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Naoki MUROTA, Hiroyuki FUJIMOTO, Hiroshi KAWAMURA
  • Publication number: 20100255384
    Abstract: A nonaqueous electrolyte secondary battery including a negative electrode containing a graphite material as the negative active material, a positive electrode containing lithium cobalt oxide as a main component of the positive active material and a nonaqueous electrolyte solution, the battery being characterized in that the lithium cobalt oxide contains a group IVA element selected from the group consisting of Ti, Zr and Hf and a group IIA element of the periodic table, the nonaqueous electrolyte solution contains 0.2-1.5% by weight of a sulfonyl-containing compound and preferably further contains 0.5-4% by weight of vinylene carbonate.
    Type: Application
    Filed: June 17, 2010
    Publication date: October 7, 2010
    Inventors: Koji Abe, Kazuhiro Miyoshi, Yasufumi Takahashi, Hiroyuki Fujimoto, Akira Kinoshita, Shingo Tode, Ikuro Nakane, Shin Fujitani
  • Patent number: 7808052
    Abstract: A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: October 5, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yoshihiro Takaishi
  • Publication number: 20100239910
    Abstract: A non-aqueous electrolyte secondary battery including a positive electrode having a positive electrode mixture layer containing a positive electrode active material, a binder, and a conductive agent, and a negative electrode having a negative electrode active material capable of intercalating and deintercalating lithium. The positive electrode active material includes a layered lithium-transition metal composite oxide represented by the compositional formula LiaNixM(1-x)O2 where 0<a?1.1, 0.5<X?1.0, and M is at least one element. The binder contains a fluororesin and a nitrile-based polymer. The amount of the nitrile-based polymer is 40 mass % or less with respect to the total amount of the binder.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 23, 2010
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shingo Tode, Katsuaki Takahashi, Yoshinori Kida, Hiroyuki Fujimoto
  • Patent number: 7799591
    Abstract: A semiconductor device comprises a first contact plug, a first structure and a second insulating layer, or comprises a first contact plug, a first structure, a protruding region and a second insulating layer. The first contact plug extends in a predetermined direction and including a step converting a cross section area of the first contact plug perpendicular to the predetermined direction discontinuously via the step in one end side. The second insulating layer is formed on side surface of a part of the first contact plug closer to the first structure than the step, or on side surfaces of the protruding region and a part of the first contact plug closer to the first structure than the step.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: September 21, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 7793764
    Abstract: A wet brake system for a vehicle including a case; an internal operation lever disposed inside the case; a hydraulic cylinder which is integrally mounted to the case and is configured to actuate the internal operation lever; and a brake mechanism configured to be operated by the actuation of the internal operation lever by the hydraulic cylinder to apply a braking force to an axle of the vehicle.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: September 14, 2010
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Hiroyuki Fujimoto, Haruo Kitai, Izumi Takagi