Abstract: A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.

Abstract: A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.

Abstract: A drain (7) comprises a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Abstract: In an inkjet recording apparatus which is equipped with a recording head having a discharge opening surface on which plural different-length discharge opening arrays are disposed in parallel, plural wipers are provided for wiping off the discharge opening surface in a direction intersecting the discharge opening arrays. Each of the plural wipers has a main wiping section corresponding to the length of the corresponding discharge opening array, notch sections capable of avoiding convex portions or concave portions located in the vicinity of both the ends of the corresponding discharge opening array, and a sub wiping section corresponding to an area other than the discharge opening array and the convex or concave portions, whereby it is possible to effectively wipe off the discharge opening surface by a simple structure and easily output a high-quality recording result by an inexpensive mechanism.

Abstract: A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls.

Abstract: The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.

Abstract: The present invention relates to a sapphire monocrystalline body to be used as the substrate for a semiconductor for electronic parts or component parts, and to a monocrystalline sapphire substrate. The invention also relates to a method for working the same. The invention is based cleavage along the plane R of the sapphire monocrystalline body which cleavage is easy to accomplish and provides a surface high in precision. The inventive process includes forming linear crack parallel or vertical to a reference plane of the substrate, with a microcrack line as a starting point, to develop a crack in a thickness direction of the body.

Abstract: A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.

Abstract: The present invention relates to a sapphire monocrystalline body to be used as the substrate for a semiconductor for electronic parts or component parts, and to a monocrystalline sapphire substrate. The invention also relates to a method for working the same. The invention is based cleavage along the plane R of the sapphire monocrystalline body which cleavage is easy to accomplish and provides a surface high in precision. The inventive process includes forming linear crack parallel or vertical to a reference plane of the substrate, with a microcrack line as a starting point, to develop a crack in a thickness direction of the body.

Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

Abstract: The present invention relates to a sapphire monocrystal body to be used as the substrate of the thin growth for the semiconductor or the like as electronic parts or component parts, and to a monocrystal sapphire substrate. The invention also relates to a method for working the same. The invention utilizes that the cleavage plane of the plane R of the sapphire monocrystal body has a smooth plane high in surface precision and is easier to cleave. For an easier dividing operation, by cleaving, of the substrate after the formation of the element such as semiconductor element, functional element, the reference plane substantially parallel or vertical to the plane R is provided on the periphery of the substrate, so as to make an index for controlling the plane R in the cleavage division. A method applies forming linear crack parallel or vertical to the reference plane of the substrate, having microcrack line as a starting point to develop the crack in the thickness direction.

Abstract: A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.

Abstract: The present invention relates to a recording apparatus provided with recording device for effecting recording on a sheet which has sheet containing device provided detachably attachably to a main body of the apparatus, sheet supporting device disposed in the sheet containing device, for supporting the sheet, lift device for lifting the sheet supporting device from the sheet containing device in operative association with an operation of attaching the sheet containing device to the main body of the apparatus, and sheet feeding device for feeding the sheet from the sheet feeding device for feeding the sheet from the sheet supporting device lifted by the lift device toward the recording device.

Abstract: In an inkjet recording apparatus which is equipped with a recording head having a discharge opening surface on which plural different-length discharge opening arrays are disposed in parallel, plural wipers are provided for wiping off the discharge opening surface in a direction intersecting the discharge opening arrays. Each of the plural wipers has a main wiping section corresponding to the length of the corresponding discharge opening array, notch sections capable of avoiding convex portions or concave portions located in the vicinity of both the ends of the corresponding discharge opening array, and a sub wiping section corresponding to an area other than the discharge opening array and the convex or concave portions, whereby it is possible to effectively wipe off the discharge opening surface by a simple structure and easily output a high-quality recording result by an inexpensive mechanism.

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Abstract: The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.

Abstract: In a serial recording apparatus having three recording modes, i.e., normal, high-quality, and high-speed recording mode, sheet feed control satisfying requirements in these modes is performed. More specifically, high-speed sheet feed control is performed in the normal or high-speed recording mode, and low-noise sheet feed control with improved precision is performed in the high-quality recording mode although the speed is low.

Abstract: A substrate for forming a semiconducting layer is provided to grow the semiconducting layer on a major surface thereof, wherein the substrate comprises a single crystal of a chemical formula of XB2 where X contains one of Ti and Zr and the major surface may preferably be substantially parallel to plane (0001) of the single crystal because the plane (0001) of the boride substrate is highly coherent to the lattices of GaN and AlN layers grown eptaxially on the substrate. The single crystal of the substrate may be a solid solution containing impurities of not more than 5%, wherein at least one of the impurities is one selected from Cr, Hf, V, Ta and Nb. Further, a semiconductor device includes the substrate of a single crystal of a chemical formula of XB2 and at least one semiconducting layer which is grown epitaxially on the substrate, the semiconducting layer including a nitride semiconductor of a chemical formula of ZN where Z is one of gallium, aluminum and indium and boron.