Abstract: The present invention relates to an image processing apparatus, method, and program which compress images so as to improve contrast without losing sharpness. An adder 33 calculates an illumination-component addition/subtraction remaining amount T (L) by an adder 25 to a multiplier 32. An adder 34 adds T (L) to an original illumination component, and calculates a gain-optimum illumination component T (L)?. An aperture controller 23 performs aperture correction which is dependent on an illumination-component level on the basis of an adaptation area determined by a reflectance-gain coefficient calculation section 35. An adder 37 adds T (L)? to the texture component after the aperture correction. Thus, a luminance signal Y2 after dynamic-range compression is obtained. An HPF 41 to an adder 43 perform LPF processing on a chroma signal of a low-band level portion. Thus, a chroma signal C2 after the dynamic-range compression is obtained. The present invention can be applied to a digital video camera.

Abstract: The present invention discloses a SiC crystal, comprising: acceptor impurities that are in a concentration greater than 5×1017 cm?3; donor impurities that are in a concentration less than 1×1019 cm?3 and greater than the concentration of the acceptor impurities. The present invention discloses a semiconductor device, comprising: a SiC fluorescent layer having acceptor impurities that are in a concentration greater than 5×1017 cm?3 and donor impurities that are in a concentration less than 1×1019 cm?3 and greater than the concentration of the acceptor impurities; and a light emission layer that is layered on the SiC fluorescent layer and emits excitation light for the SiC fluorescent layer.

Abstract: A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract: Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

Abstract: Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.

Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.

Abstract: Flash memory devices and methods for fabricating the same are provided. A method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a P-type silicon substrate and implanting an impurity dopant into the substrate substantially between the first gate stack and the second gate stack to form an impurity-doped region of the substrate. A channel region underlies the first gate stack adjacent to the impurity-doped region. An intrinsically tensile-stressed insulating member is formed between the first and the second gate stacks and overlying the impurity-doped region. The tensile-stressed insulating member causes a uniaxial lateral tensile stress to be transmitted to the first channel region. A word line is formed overlying the intrinsically tensile-stressed insulating member and in electrical contact with the first gate stack and the second gate stack.

Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).

Abstract: Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

Abstract: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract: Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element.

Abstract: Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.

Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Abstract: According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Abstract: Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.