Abstract: A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.

Abstract: Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

Abstract: An image processing apparatus and an image processing method are provided that enable accurate detection of color shift occurring due to chromatic difference of magnification. An image processing apparatus includes an image signal extraction unit to extract at least a part of an image signal from image data based on signal characteristics of the image signal, an edge detection unit to detect an edge portion in an image by the image data from a detection target that is the extracted image signal based on a luminance value of the image signal, and a color shift amount detection unit to detect a color shift amount by calculating a correlation of at least two color components contained in the image signal according to a distance from a reference position in the image.

Abstract: Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

Abstract: Durability of a recording apparatus is enhanced. The recording apparatus includes: a carriage that carries a recording head which discharges a liquid onto a recording medium; and a guide unit that supports the carriage so as to be freely movable. The carriage has a first sliding surface and a second sliding surface. The first sliding surface is slidable on the guide unit, and the second sliding surface is displaceable with respect to the carriage and slidable on the guide unit. The recording apparatus is switchable between a first condition in which the guide unit and the first sliding surface are in contact with each other, and a second condition in which the guide unit and the second sliding surface are in contact with each other.

Abstract: A first conveying mechanism includes an intermediate conveying roller for conveying a recording sheet, an intermediate conveying roller shaft for supporting the intermediate conveying roller, an intermediate conveying roller drive mechanism for rotationally driving the intermediate conveying roller shaft, and a roller control mechanism for controlling movements of the intermediate conveying roller relative to the intermediate conveying roller shaft.

Abstract: A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

Abstract: A printer includes a set cover pivotally movably provided on a carriage. The cover can be set in a closed state in which the cover presses a head of the cartridge housed in the housing portion and an open state in which the cover opens the housing portion when the cartridge is replaced. A release lever is subjected to a bias force so as to protrude from an inner wall surface of the housing portion. The release lever is movable against the bias force. The release lever comes into contact with an end of the cartridge which faces the bottom surface when the cartridge is inserted into the housing portion. The release lever contacts the rear surface of the cartridge housed in the housing portion. The bias force is stronger when the cover is in the open state than when the cover is in the closed state.

Abstract: An image-pickup device includes a solid-image-pickup element which can select between an ordinary mode wherein all of a plurality of pixel signals are sequentially read and at least one pixel-addition mode wherein the pixel signals corresponding to same-color filters are added and output; a defective-information-storage unit which stores position information of a defective pixel on the solid-image-pickup element in the ordinary mode; a signal-correction unit which corrects a pixel signal of a picked-up-image signal based on the position information; and a position-information conversion unit that converts the position information when the pixel-addition mode is selected so that the position information agrees with information about a pixel arrangement, the pixel-arrangement information corresponding to the picked-up-image signal generated in the pixel-addition mode, and that transmits the converted position information to the signal-correction unit.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: A driving circuit that reduces chip size of a source driver while maintaining image quality when image data is configured by multiple bits. The source driver provided in connection with a timing controller that converts image data into color data. The source driver displays an image by controlling pixel density of a liquid crystal panel. The source driver is divided into plural regions in units of pseudo linear elements to perform a gamma correcting operation based on a gamma characteristic. In the source driver a GMA voltage for each region is divided by resistive elements arranged between input signal lines. With respect to variation of plural divided GMA voltages, variation of the maximum high density region becomes coarser than variation of the maximum low density region in compliance with visual sensitivity of the density, thus reducing the number of input data lines of the source driver.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Abstract: Noise reduction is performed on the basis of characteristics of an image in a detection range. A noise reduction block 4? performs a second-order differentiation process and a symmetry process to decide adjacent pixels with which noise reduction is preformed for an attention pixel. With the pixel level of the attention pixel in the detection range and the pixel levels of adjacent pixels used for noise reduction, an arithmetic mean processing section 16 calculates a mean value. A median filter 17 selects a median value. With the number of pixels used for noise reduction, it is determined whether the image in the detection range contains a flat portion, a ramp portion, or an edge. The mean value and the median value are weight-added with a weighted coefficient that are changed on the basis of characteristics of the image. The result is substituted for the level of the attention pixel.

Abstract: A wireless LAN terminal includes a wired LAN interface, a wireless LAN interface and a bridge unit. The bridge unit detects that a terminal apparatus connected with the wired LAN interface moves to a position under different wireless LAN equipment and learns a MAC address of the terminal apparatus which moves.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: An image processing apparatus includes an image clipping unit, a feature extracting unit, a candidate identifying unit, and a detecting unit. The image clipping unit clips a window image from a predetermined position of an original image. The feature extracting unit extracts a feature value of the window image on the basis of a predetermined criterion. The candidate identifying unit determines, on the basis of the feature value, whether the window image satisfies a predetermined condition for a candidate including a detection target. The detecting unit determines whether the window image includes the detection target if the window image satisfies the predetermined condition.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.