Abstract: Durability of a recording apparatus is enhanced. The recording apparatus includes: a carriage that carries a recording head which discharges a liquid onto a recording medium; and a guide unit that supports the carriage so as to be freely movable. The carriage has a first sliding surface and a second sliding surface. The first sliding surface is slidable on the guide unit, and the second sliding surface is displaceable with respect to the carriage and slidable on the guide unit. The recording apparatus is switchable between a first condition in which the guide unit and the first sliding surface are in contact with each other, and a second condition in which the guide unit and the second sliding surface are in contact with each other.

Abstract: An image processing method includes the steps of calculating, with respect to a processing-target pixel in an input image signal, a concentric aberration correction amount for concentric aberration that is a component of magnification chromatic aberration, the concentric aberration causing a color shift to occur in a concentric manner from the center of an image, calculating, with respect to the processing-target pixel, a uniform aberration correction amount for uniform aberration that is a component of magnification chromatic aberration, the uniform aberration causing a color shift direction and a color shift amount to uniformly occur on a whole image, and correcting a pixel value of the processing-target pixel on the basis of the calculated concentric aberration correction amount and the calculated uniform aberration correction amount.

Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

Abstract: A first conveying mechanism includes an intermediate conveying roller for conveying a recording sheet, an intermediate conveying roller shaft for supporting the intermediate conveying roller, an intermediate conveying roller drive mechanism for rotationally driving the intermediate conveying roller shaft, and a roller control mechanism for controlling movements of the intermediate conveying roller relative to the intermediate conveying roller shaft.

Abstract: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract: First humidified gas is supplied from a first supply port to a sheet to be conveyed to increase the moisture content of the sheet. Second humidified gas is supplied to a space where nozzles of the inkjet recording head are exposed, from a second supply port provided at a position closer to the inkjet recording head than the first supply port to increase the atmosphere humidity of the space. The part of the sheet of which the moisture content has been increased is made to enter the space where the atmosphere humidity has been increased, and recording is performed. When a conveyance operation stops, the quantity of flow or humidity of the first humidified gas is reduced. In resupplying a temporarily returned sheet, the amount of moisture to be provided by the first humidified gas is set in accordance with regions of the sheet.

Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: In a printing system capable of selectively performing duplex printing and simplex printing, a switching unit switches a sheet travel path between a first path and a second path parallel to each other, and reverses the sides of a sheet that passes along the first path. In the duplex printing, a sheet is printed on a first side by a first printing apparatus, reversed by the switching unit, and printed on a second side reverse of the first side by a second printing apparatus. In the simplex printing, only one side of a sheet is printed by the first printing apparatus and/or second printing apparatus. First and second input units introduce sheets into the first and second paths, respectively; and first and second output units receive printed sheets that have traveled along the first and/or second paths.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: A manual pressurization electronic sphygmomanometer includes a specific component detection unit for detecting a synthetic wave of a manual fluctuation wave and a pressure pulse wave as a specific component from a cuff pressure signal obtained during pressurization; a derivation processing unit for deriving a pressurization target value based on the detection result of the specific component detection unit; and a display unit for notifying to urge pressurization up to the pressurization target value. The derivation processing unit calculates a pulse wave component based on the waveform before and after the specific component and the waveform of the specific component, and determines a value obtained by adding a predetermined value to the systolic blood pressure value estimated based on the amplitude of the pulse wave component as the pressurization target value.

Abstract: SiC single crystal that includes a first dopant functioning as an acceptor, and a second dopant functioning as a donor is provided, where the content of the first dopant is no less than 5×1015 atoms/cm3, the content of the second dopant is no less than 5×1015 atoms/cm3, and the content of the first dopant is greater than the content of the second dopant. A manufacturing method for silicon carbide single crystal is provided with the steps of: fabricating a raw material by mixing a metal boride with a material that includes carbon and silicon; vaporizing the raw material; generating a mixed gas that includes carbon, silicon, boron and nitride; and growing silicon carbide single crystal that includes boron and nitrogen on a surface of a seed crystal substrate by re-crystallizing the mixed gas on the surface of the seed crystal substrate.

Abstract: A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.

Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: A recording apparatus having a function of sorting recording sheets is reduced in size and cost. The recording apparatus conveys the recording sheets, records on the recording sheets, discharges the recording sheets, and sorts the discharged recording sheets. The recording apparatus includes: a movable carriage that holds a recording head for recording on the recording sheets; and a sorting mechanism that controls positions of the recording sheets so that the discharged recording sheets are sorted, and the sorting mechanism is configured to be operated by the carriage and sort the recording sheets in accordance with a position of the carriage.

Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.