Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.

Abstract: Provided is an in-cell touch panel having improved display quality. An opposite substrate relating to one embodiment of the present invention is provided with a black matrix, first electrodes, which are disposed in the Y direction, and second electrodes, which are disposed in the X direction. The first electrodes and the second electrodes are formed such that the boundaries therebetween are positioned in regions that coincide with the black matrix in a planar view.

Abstract: A touchscreen panel according to an embodiment of the present invention includes a transparent substrate (101); a first electrically conductive layer (12) supported on the transparent substrate, the first electrically conductive layer including a plurality of sensing electrodes (12S) extending along a first direction; and a second electrically conductive layer (14) including a plurality of driving electrodes (14D) extending along a second direction intersecting the first direction, the plurality of driving electrodes being electrically insulated from the plurality of sensing electrodes. The plurality of sensing electrodes and the plurality of driving electrodes define a sensor array region (10A), the sensor array region including a plurality of sensor portions (10S) arranged in a matrix array. The first electrically conductive layer further includes a plurality of lead lines (12Dt) extending essentially in parallel to the first direction within the sensor array region.

Abstract: A display device with a touch sensor (100) according to an embodiment of the present invention includes: a pixel substrate (20) including a plurality of pixel electrodes (2); a counter substrate (10) opposing the pixel substrate (20); a black matrix (8) extending in a first direction and in a second direction different from the first direction; and a touch sensor electrode (6) extending in the first direction.

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Abstract: A touch panel substrate (5) provided with position detecting electrodes (first electrodes (12) and second electrodes (13)) includes a black matrix (17) which is made of an electrically conductive material and is electrically connected to a counter electrode (19). This provides (i) a touch panel substrate which is high in position detection performance and capable of carrying out a stable position detecting operation and which is used in an in-cell touch panel, and (ii) a display panel including such a touch panel substrate.

Abstract: A stack of material layers includes first material layers, second material layers located between a respective pair of an overlying first material layer and an underlying first material layer, and at least one temporary material layer located between a respective pair of an overlying first material layer and an underlying first material layer. After formation of a memory opening and a memory stack structure, at least one first backside recess is formed by removing the at least one temporary material layer and adjoining portions of a memory film. A physically exposed portion of a semiconductor channel is doped with electrical dopants to form a doped semiconductor channel portion. Second backside cavities are formed by removal of the second material layers. The backside cavities are then filled with a dielectric liner and electrically conductive layers, such as select and control gate electrodes of a memory device.

Abstract: A continuously variable transmission includes a shaft, first and second rotary members, a sun roller, a carrier, planetary balls, a gear shifter for changing a gear ratio between input and output by tilting each of the planetary balls, a casing for accommodating these elements, and a lubricating oil supply opening for supplying lubricating oil into the casing. The casing includes a discharge opening for discharging the lubricating oil to the outside of the casing. The discharge opening is provided in a wall of the casing in an axial direction of the shaft and radially outside the lubricating oil supply opening. As seen in the axial direction, the discharge opening is formed either at a position that crosses a contact section between the planetary ball and each of the first and second rotary members or an auxiliary contact section, or radially outside the contact section or the auxiliary contact section.

Abstract: A continuously variable transmission includes: a transmission shaft; first to fourth power transmission elements that have a first rotation center axis coaxial with the transmission shaft; a plurality of rolling members that has a second rotation center axis; a transmission device configured to change a gear ratio between an input side and an output side by tilting each of the rolling members; a rotary shaft that is coupled with one of the first and second power transmission elements, and is provided with a cylindrical section; an annular member that is coupled with the rotary shaft, and configured to form an annular oil reservoir formed of lubricating oil; and a scraping up section configured to scrape up the lubricating oil by rotating in the circumferential direction.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: An impulse voltage generator uses a predetermined rectangular waveform signal and a high voltage to generate an impulse voltage. The high voltage is obtained by boosting an instruction voltage of the rectangular waveform signal on a per-cycle basis. A partial discharge frequency calculation section receives detection signals based on partial discharges occurring in an object to be measured by the application of the impulse voltage and counts the detection signal on a per-cycle basis as a partial discharge frequency. An application voltage signal observation circuit observes an application voltage signal indicating the impulse voltage applied to the object to be measured. In a first cycle in which the partial discharge frequency reaches a specified frequency or more, a voltage value acquiring section sets, as a partial discharge starting voltage, the peak value of the voltage indicated by the application voltage signal output from the application voltage signal observation circuit.

Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.

Abstract: A sense line drive circuit (24) (i) receives signals passing through capacitances and outputted via sense lines (SeL1, SeL2 . . . and SeLn) during a period other than a period during which image data is sequentially written to a plurality of pixels in a liquid crystal panel and (ii) detects where, in a plurality of portions where the sense lines (SeL1, SeL2 . . . and SeLn) and drive lines (DL2, DL2 . . . and DLn) are close to each other, a detection target is present.

Abstract: A semiconductor layer for an active element included in each of a plurality of pixels in a display section is constituted by an oxide layer containing at least one element selected from the group consisting of In, Ga, and Zn. There is provided, for the display section, a liquid crystal panel's timing controller (13) configured to carry out control so that (i) a length of a first period during which image data is written is not more than twice that of the second period and/or (ii) one (1) frame period is longer than 16.7 msec.

Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.