Abstract: A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.

Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

Abstract: A touchscreen panel according to an embodiment of the present invention includes a transparent substrate (101); a first electrically conductive layer (12) supported on the transparent substrate, the first electrically conductive layer including a plurality of sensing electrodes (12S) extending along a first direction; and a second electrically conductive layer (14) including a plurality of driving electrodes (14D) extending along a second direction intersecting the first direction, the plurality of driving electrodes being electrically insulated from the plurality of sensing electrodes. The plurality of sensing electrodes and the plurality of driving electrodes define a sensor array region (10A), the sensor array region including a plurality of sensor portions (10S) arranged in a matrix array. The first electrically conductive layer further includes a plurality of lead lines (12Dt) extending essentially in parallel to the first direction within the sensor array region.

Abstract: A communication device including a device-side antenna 30 for wireless communication with an IC card 10 including a card-side antenna 11 wound in a rectangular form. The antenna 30 is formed in one or multiple loops. During the wireless communication with the IC card 10 having an inner perimeter with a long dimension of 69 mm and a short dimension of 38 mm at a distance of 25 mm, an inner perimeter of the antenna 30 is formed at a position at which intensity H of a magnetic field produced by the card-side antenna 11 in a direction perpendicular to a surface on which the antenna 30 is disposed is in a range expressed by inequation (1): 0.037I/4?<H<0.063I/4???(1) where I is a current of the card-side antenna [A] and ? is pi.

Abstract: A display device with a touch sensor (100) according to an embodiment of the present invention includes: a pixel substrate (20) including a plurality of pixel electrodes (2); a counter substrate (10) opposing the pixel substrate (20); a black matrix (8) extending in a first direction and in a second direction different from the first direction; and a touch sensor electrode (6) extending in the first direction.

Abstract: A transparent antenna 17 is provided with: an antenna body portion 18 having a ring-shape and configured to generate a magnetic field at the center thereof; a lead-out wire portions 19 led out of the antenna body portion 18, the lead-out wire portions 19 including a large-width portions 23 having a line width greater than a line width of the antenna body portion 18.

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

Abstract: In the present invention, a substrate is placed at a predetermined position on a substrate support even though the substrate is deviated on a substrate transfer unit. There is provided a substrate processing apparatus that includes a process chamber, a transfer chamber accommodating a substrate transfer unit, a substrate detecting unit, a memory unit configured to store a first reference position information, a second reference position information and a substrate reference position information and a controller configured to generate a detected position information representing a position of a substrate being transferred in the transfer chamber based on a detection result and to control the substrate transfer unit to place the substrate based on the detected position information, the first reference position information, the substrate reference position information and a difference between the first reference position information and the second reference position information.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: A communication device including a device-side antenna 30 for wireless communication with an IC card 10 including a card-side antenna 11 wound in a rectangular form. The antenna 30 is formed in one or multiple loops. During the wireless communication with the IC card 10 having an inner perimeter with a long dimension of 69 mm and a short dimension of 38 mm at a distance of 25 mm, an inner perimeter of the antenna 30 is formed at a position at which intensity H of a magnetic field produced by the card-side antenna 11 in a direction perpendicular to a surface on which the antenna 30 is disposed is in a range expressed by inequation (1): 0.037I/4?<H<0.063I/4???(1) where I is a current of the card-side antenna [A] and ? is pi.

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Abstract: A display device (1) includes a display panel (12), a touch panel (14) for detecting contact of a target object with a display region (P) of the display panel (12) or approach thereof to the display region (P), and a casing (17) containing the display panel (12) and the touch panel (14), a minimum distance (d) between the touch panel (14) and an outside surface (A) being not larger than a detectable distance, within which the touch panel (14) is capable of detecting the contact of the target object with the outside surface (A) or the approach thereof to the outside surface (A).

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Abstract: A display device is provided in which a configuration of first electrodes (4) in a first area (R1) that overlaps a display area (AA) of a touch panel (2), and a configuration of first electrodes (6) in a second area (R2) outside the first area, are different from each other. In the second area (R2), at least one electrode pad (6-1a, 6-2a) of the first electrodes (6) is arranged so as to be opposed to one second electrode (7a).

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Abstract: A crystal display device 10 includes TFTs, pixel electrodes, common electrodes, an array board, a CF board, detection electrodes, drive electrodes , a driver, a row control circuit, and a touch controller. The detection electrodes are included in the CF board. The drive electrodes are included in the CF board. The driver and the row control circuit are included in a display driver portion for supplying scan signals and data signals to the TFTs for display driving. The touch controller supplies drive signals to the drive electrodes and detects position detection signals output by the detection electrodes to perform position detection control. The touch controller supplies the drive signals to the drive electrodes to drive the drive electrodes in a scan writing period in which the scan signals are supplied to the TFTs by at least the row control circuit in the display driver portion to drive the TFTs.

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.