Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.

Abstract: A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

Abstract: An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening.

Abstract: A touch panel is realized that is able to decrease the amount of dead space at the periphery of the touch panel and that has highly accurate touch panel sensitivity. In a touch panel, Y direction conductive patterns are arranged so as to be separated from wiring patterns in Y direction conductive pattern regions between electrode units of X direction conductive patterns. As a result, in this conductive sheet, it is possible to appropriately prevent the occurrence of parasitic capacitance resulting from the Y direction conductive patterns and the wiring patterns. Therefore, in a touch panel device or the like that uses such a touch panel, it is possible to effectively prevent the generation of noise that overlaps sense signals as a result of the above-mentioned parasitic capacitance, thereby making it possible to realize highly accurate touch panel sensitivity.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

Abstract: Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.

Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding.

Abstract: A distortion compensation apparatus including: an amplifier configured to amplify an input signal including a transmission signal and an impulse signal, the transmission signal being converted to a radio frequency signal for transmission, the impulse signal being not converted to a radio signal for transmission, a memory configured to store a plurality of distortion compensation coefficients for compensating distortion to the input signal, each of the plurality of distortion compensation coefficients being associated with an amplitude of the input signal, and a processor configured to select a distortion compensation coefficient from the plurality of distortion compensation coefficients based on an amplitude of the impulse signal included in the input signal, and update the selected distortion compensation coefficient based on the amplified impulse signal include in the amplified input signal.

Abstract: A continuously variable transmission includes: first to third power transmission components; a rolling component; a support shaft for the rolling component; a first guide member that includes a first guide portion for guiding a first protrusion portion of the inserted support shaft; a gear shift member that includes a gear change portion; a first actuator which tilts each rolling component by moving each second protrusion portion along the gear change portion with rotation of the gear shift member at a time an input-output gear ratio is changed; a second guide member that includes a second guide portion for guiding a second protrusion portion of the inserted support shaft; and a second actuator which prohibits rotation of the second guide member during reverse rotation of the first and second power transmission components and allows rotation of the second guide member during normal rotation of the first and second power transmission components.

Abstract: A touch panel includes: a first substrate; a second substrate disposed on a viewer side of the first substrate; a liquid crystal layer provided between the first substrate and the second substrate; a plurality of pixel electrodes and a common electrode for applying a voltage to the liquid crystal layer; and a plurality of detection electrodes and a plurality of driving electrodes for a touch sensor. The first substrate includes: a first transparent substrate; and the plurality of pixel electrodes, which are formed on the liquid crystal layer side of the first transparent substrate. The second substrate includes: a second transparent substrate; and the plurality of driving electrodes and the plurality of detection electrodes formed on the liquid crystal layer side of the second transparent substrate. The touch panel does not include a conductive layer on the viewer side of the second transparent substrate.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

Abstract: A gas supply method includes controlling communication between first and second gas pipes and a diffusion chamber using first and second valves; controlling discharge of gas within the first and second gas pipes using third and fourth valves connected upstream from the first and second valves; and controlling communication between an exhaust pipe and the diffusion chamber using a fifth valve. The gas supply method further includes a first pressurization step of closing the first valve and the third valve before starting a first step and pressurizing a first gas within the first gas pipe; a second pressurization step of closing the second valve and the fourth valve before starting a second step and pressurizing a second gas within the second gas pipe; and an exhaust step of opening the fifth valve upon starting the first step and the second step, and discharging gas within the diffusion chamber.

Abstract: Provided are a substrate processing apparatus, a method of processing a substrate, a method of manufacturing a semiconductor device, and a non-transitory computer readable recording medium storing a program for performing the method of manufacturing the semiconductor device, that are capable of improving manufacturing throughput of the apparatus. The substrate processing apparatus includes a substrate to be processed, a transfer chamber under a vacuum atmosphere, a substrate transfer unit installed at the transfer chamber and configured to transfer the substrate, at least two process chambers installed near the transfer chamber and configured to process the substrate, at least two gate valves installed between the transfer chamber and the at least two process chambers, and a control unit configured to control the substrate transfer unit and the at least two gate valves, wherein the control unit opens and closes the at least two gate valves while the substrate transfer unit transfers the substrate.