Patents by Inventor Hiroyuki Uchiyama

Hiroyuki Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6833331
    Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: December 21, 2004
    Assignees: Hitachi Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayoshi Saito, Katsuhiko Hotta, Masayoshi Hirasawa, Masayuki Kojima, Hiroyuki Uchiyama, Hiroyuki Maruyama, Takuya Fukuda
  • Patent number: 6828242
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: December 7, 2004
    Assignees: Hitachi, Ltd., NEC Corporation, NEC Electronics Corporation
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Publication number: 20040235289
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 25, 2004
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Patent number: 6809479
    Abstract: A self-ballasted electrodeless discharge lamp of the invention is provided with a discharge vessel filled with discharge gas, the discharge vessel having a cavity portion, a coil inserted into the cavity portion of the discharge vessel, a ballast circuit for supplying high frequency power to the coil, and a lamp base that is electrically connected to the ballast circuit, wherein the discharge vessel, the coil, the ballast circuit, and the lamp base are configured as a single unit, and a reflective tape for reflecting light that is radiated from the discharge gas and emitted from inside the discharge vessel to its cavity portion side is wound around the coil.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: October 26, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoko Shimomura, Koji Miyazaki, Satoshi Kominami, Kohei Enchi, Hiroyuki Uchiyama
  • Publication number: 20040209431
    Abstract: An active region 1 has diffusion layers 6a to 8a sandwiched by plural word-lines. The diffusion layer 6a sandwiched by word-lines 2 and 3 locates at a center of the active region 1 and connects to a bit-line through a contact. The diffusion layers 7a and 8a sandwiched by word-lines 2 and 3 and both sides of the active region 1 respectively are connected to capacitor portions. A cell structure is formed of two cell transistors. One cell transistor has the word-line 2 as a gate and the diffusion layers 6a and 7a as source and drain, respectively. The other cell transistor has the word-line 3 as a gate and the diffusion layers 6a and 8a as a source and a drain, respectively. The diffusion layers 7a and 8a placed outside of the active region 1 are n-type and have high carrier concentration of n-type at the region separated from word-lines than to the region close to the word-lines 2 and 3. A p-type substrate exhibits low concentration at the region outside the word-lines.
    Type: Application
    Filed: July 24, 2003
    Publication date: October 21, 2004
    Applicant: Elpida Memory, Inc.
    Inventors: Kiyonori Oyu, Atsushi Ogishima, Hiroyuki Uchiyama, Keizo Kawakita, Masahito Suzuki
  • Publication number: 20040185914
    Abstract: A cellular phone has a black-and-white LCD that displays characters and communication information and a color LCD that displays an image. The image and the characters are displayed on the separate LCDs. Thus, the characters are not superimposed on the image, and they are easy to see. When the image is not needed (the user is not using the phone or the user is talking on the phone), only the black-and-white LCD displays the characters and the color LCD is turned off to save energy.
    Type: Application
    Filed: April 2, 2004
    Publication date: September 23, 2004
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Hiroshi Ohmura, Ko Aosaki, Hiroyuki Uchiyama, Seiji Takada, Hiroshi Soma, Chiaki Fujii, Seimei Ushiro
  • Publication number: 20040173838
    Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.
    Type: Application
    Filed: March 16, 2004
    Publication date: September 9, 2004
    Applicant: Renesas Technology Corporation.
    Inventors: Teruhisa Ichise, Hiroyuki Uchiyama, Masayuki Suzuki
  • Patent number: 6780757
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20040140495
    Abstract: A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 22, 2004
    Inventors: Hiroyuki Uchiyama, Atsushi Ogishima, Shoji Shukuri
  • Patent number: 6762449
    Abstract: A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: July 13, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Uchiyama, Atsushi Ogishima, Shoji Shukuri
  • Patent number: 6746938
    Abstract: A method manufactures a semiconductor device by forming at least an active device on a principal surface of a semiconductor substrate; etching the semiconductor substrate to thereby form a viahole adjacent to an active region where the active device is formed; and forming a plated wiring including the inner wall of the viahole and extending to an electrode of the active device on the surface of the substrate. This method uses a photo sensitive polyimide material as an etching mask in the step of forming a viahole and can thereby form a fine viahole in a high yield.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: June 8, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Uchiyama, Takashi Shiota
  • Patent number: 6740924
    Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: May 25, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Teruhisa Ichise, Hiroyuki Uchiyama, Masayuki Suzuki
  • Publication number: 20040063276
    Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.
    Type: Application
    Filed: August 20, 2003
    Publication date: April 1, 2004
    Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin?apos;ichiro Kimura, Kazuyuki Hozawa
  • Publication number: 20030199161
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Application
    Filed: May 7, 2003
    Publication date: October 23, 2003
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20030183860
    Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 2, 2003
    Inventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
  • Publication number: 20030162564
    Abstract: The peripheral surface of columnar rotary body is formed to have a light-entrant opening, and the bottom of the rotary body is formed to have an emergent-light opening. Light that has entered from the light-entrant opening is introduced to the emergent-light opening by a first mirror. Light that has impinged upon the rotary body is introduced from the emergent-light opening to a first half body that constructs the main unit of a portable telephone. A second mirror is disposed within the first half body, and light that has emerged from the rotary body is introduced to the photoreceptor surface of a C-MOS sensor by the second mirror. Since the rotary body and the first half body are not connected by a cord or the like, the rotary body can be turned through any angle to enable imaging at any angle.
    Type: Application
    Filed: February 5, 2003
    Publication date: August 28, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Soichiro Kimura, Naoyuki Nishino, Hiroyuki Uchiyama, Takaaki Kotani
  • Patent number: 6603162
    Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: August 5, 2003
    Assignees: Hitachi, LTd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
  • Publication number: 20030137642
    Abstract: Temperature is detected by a temperature sensor disposed near a recording head. When the detection result is a temperature that is higher than room temperature, an appropriate movement amount of the recording head is calculated from a relation between response speed of the temperature sensor and a LED light amount, and a moving speed of the recording head is controlled. When the result of the detection by the temperature sensor is a temperature that is lower than room temperature, an appropriate exposure amount is calculated from the relation between the response speed of the temperature sensor and the LED light amount, and the amount of light emitted by LEDs is controlled.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 24, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Hiroyuki Uchiyama, Mutsumi Naruse, Soichiro Kimura
  • Publication number: 20030132476
    Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.
    Type: Application
    Filed: December 16, 2002
    Publication date: July 17, 2003
    Inventors: Teruhisa Ichise, Hiroyuki Uchiyama, Masayuki Suzuki
  • Publication number: 20030122946
    Abstract: In order to reduce the frame rate, when all photodiodes contributing to output of a video signal in a CMOS image sensor must be simultaneously exposed (at the timing of strobe flashing &Dgr;ts), as in a case where strobe is flashed, readout pixels composing the CMOS type image sensor are thinned such that the number of photodiodes contributing to the video signal outputted from the CMOS type image sensor is reduced. A time period &Dgr;tp2 required for processing (of the video signal caused by a row of photodiodes) in an analog processing circuit connected to the succeeding stage of the CMOS type image sensor is shortened, thereby reducing the frame rate.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Naoyuki Nishino, Hiroyuki Uchiyama, Takaaki Kotani, Soichiro Kimura