Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: A semiconductor device of the present invention comprises a memory cell area having memory cells arranged in an array form, each of which includes a capacitor for storing data and a peripheral circuit area for accessing the memory cell area. The peripheral circuit area is provided with a plurality of wiring layers and each of the memory cells has a capacitor. The capacitor is comprised of a plate electrode, a capacitive insulating film formed on a side wall of an opening formed through the plate electrode, and a storage electrode embedded in the opening in which the capacitive insulating film is formed on the side wall, such that the plate electrodes, the capacitive insulating films, and the storage electrodes of the memory cells are arranged in correspondence to the plurality of wiring layers, and the storage electrodes are connected to one another.

Abstract: The MEMS switch comprises a first anchor formed over a substrate, a first spring connected to the first anchor, an upper electrode which is connected to the first spring and makes a motion above the substrate, elastically deforming the first spring, a lower electrode formed over the substrate, positioned under the upper electrode, a second spring connected to the upper electrode, and a second anchor connected to the second spring. When voltage is applied between the upper and lower electrodes and the upper electrode makes a downward motion, the second anchor is brought into contact with the substrate. As a result, the second spring is elastically deformed. When the upper electrode is subsequently brought into contact with the lower electrode, thereby the upper and lower electrodes are electrically connected. The first and second anchors, first and second springs, and upper electrode are formed of identical metal in integral structure.

Abstract: A cellular phone is connected to a portable printer which uses an instant print film through connectors, and the printer prints an image according to image data stored in the cellular phone. The cellular phone can display the image to be printed on its LCD. The user can input information for the printing with push buttons of the cellular phone, and display the information on the LCD. Thus, the portable printer does not need an LCD and push buttons, and therefore the printer is small, light and inexpensive.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: The present invention provides a compact printer that can print images of high quality even if the images are printed successively. A temperature at the time of turn-on is detected by a temperature sensor, and a CPU estimates the temperature of an exposure head at the start of exposure based on the detected temperature. The CPU creates print data by referring to a look-up table in accordance with the estimated temperature and drives the exposure head in accordance with the print data, thereby forming a latent image on an instant film sheet.

Abstract: In order to reduce the frame rate, when all photodiodes contributing to output of a video signal in a CMOS image sensor must be simultaneously exposed (at the timing of strobe flashing ?ts), as in a case where strobe is flashed, readout pixels composing the CMOS type image sensor are thinned such that the number of photodiodes contributing to the video signal outputted from the CMOS type image sensor is reduced. A time period ?tp2 required for processing (of the video signal caused by a row of photodiodes) in an analog processing circuit connected to the succeeding stage of the CMOS type image sensor is shortened, thereby reducing the frame rate.

Abstract: Temperature is detected by a temperature sensor disposed near a recording head. When the detection result is a temperature that is higher than room temperature, an appropriate movement amount of the recording head is calculated from a relation between response speed of the temperature sensor and a LED light amount, and a moving speed of the recording head is controlled. When the result of the detection by the temperature sensor is a temperature that is lower than room temperature, an appropriate exposure amount is calculated from the relation between the response speed of the temperature sensor and the LED light amount, and the amount of light emitted by LEDs is controlled.

Abstract: A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A semiconductor device and a manufacturing method thereof which enable to secure high yield and increase the capacity of a capacitor are provided. The semiconductor device according to the present invention includes: a plurality of capacitor layers laminated, each capacitor layer including a plurality of storage electrodes, a capacity insulating film covering the surface of the storage electrodes, and a plate electrode provided between the storage electrodes, wherein the plate electrode of each of the laminated capacitor layers are electrically connected to each other and the corresponding storage electrode of each of the laminated capacitor layers are electrically connected to each other.

Abstract: This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

Abstract: In a microwave integrated circuit, a capacitance element is connected to the input side of each active device to remove noise signals. These capacitance elements and the wires, etc. for them have prevented the miniaturization of the chip since they require large areas on the chip. Further, in the case of a semiconductor active device, particularly a field-effect transistor, the gate metal formed on the step portions of the mesa may break or the gate metal may come into contact with the active layer during the “mesa-type device separation” process, resulting in degradation in the characteristics. To overcome the above problems, the present invention provides a device configuration in which: the capacitance element is formed right under one terminal of the semiconductor device; and one of the two electrodes of the capacitance element is connected to the underside of the terminal.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.