Patents by Inventor Hisashi Adachi

Hisashi Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040263255
    Abstract: In a power amplifier of the present invention, distributed constant lines 105a and 105b have a total line length corresponding to a ½ wavelength of a fundamental wave so as to invert the phase of a fundamental wave component of a first signal amplified by a first amplification element 102a. A series resonant circuit 106 is connected a tone end between the distributed constant lines 105a and 105b, which invert the phase of a second-order harmonic component, so as to be in parallel connection with the distributed constant lines 105a and 105b. Further, the series resonant circuit 106 is connected at the other end to an output side of the second amplification element 102b. The series resonant circuit 106 resonates with a second-order harmonic frequency, thereby canceling out the second-order harmonic component.
    Type: Application
    Filed: June 22, 2004
    Publication date: December 30, 2004
    Inventors: Shigeru Morimoto, Hisashi Adachi
  • Patent number: 6826418
    Abstract: The invention provides a radio circuit realizing a desired receiving characteristic even when a strong-level interfering wave is received and operating with small power when no interfering wave is received. The radio circuit comprises a receiving circuit for selecting a signal having a desired frequency from received signals and demodulating the signal, an input-power detector for detecting power P1 of the receiving circuit, a received-power detector for detecting power P2 of a signal selected by the receiving circuit, and a reception control circuit for controlling the receiving circuit. The reception control circuit controls the receiving circuit at a low distortion by increasing the power consumption of a circuit included in the receiving circuit and thereby expanding the linear operation range when the power P1 detected by the input-power detector is larger than a predetermined value t1 and the power P2 detected by the input-power detector is smaller than a predetermined value t3.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: November 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Adachi, Masanori Iida, Hiroyuki Asakura
  • Publication number: 20040232988
    Abstract: In order to enhance a reverse isolation characteristic of a differential amplifier, which is used as, for example, an RF amplifier or a local amplifier of a mobile telephone, the present invention provides a differential amplifier which includes a differential amplification circuit 10 for amplifying a difference in potential between two input signals in reverse phase with each other, which are inputted into Port1 and Port2, and for outputting two output signals in reverse phase with each other from Port3 and Port4; a feedback capacitor 7a connected between Port1 and Port4; and a feedback capacitor 7b connected between Port2 and Port3. Signals for canceling feedback signals are inputted into input terminals via the feedback capacitors 7a and 7b, respectively, whereby it is possible to the reverse isolation characteristic of the differential amplifier.
    Type: Application
    Filed: May 19, 2004
    Publication date: November 25, 2004
    Inventors: Toshifumi Nakatani, Hisashi Adachi
  • Publication number: 20040227608
    Abstract: A transformer element 1 is formed on a semiconductor substrate using first and second wiring layers arranged parallel to each other in a vertical direction, and includes a first inductor 2 and a second inductor 3. The first and second inductors 2 and 3 are each provided using the first and second wiring layers such that if projected into one of the first and second wiring layers either along a vertical upward direction or a vertical downward direction, outlines of a projection form a symmetrical shape with respect to a predetermined reference plane, and portions corresponding to intersections between the outlines of the projection on the wiring layer are formed so as to be out of contact with each other.
    Type: Application
    Filed: May 12, 2004
    Publication date: November 18, 2004
    Inventors: Toshifumi Nakatani, Hisashi Adachi
  • Publication number: 20040180633
    Abstract: The radio communication apparatus comprising an antenna, a transmitting circuit of outputting a transmitting signal in a first frequency band, a duplexer, connected to the antenna and having a single-phase input terminal and a balanced output terminal, of conveying the transmitting signal inputted to the single-phase input terminal to the antenna and outputting a receiving signal in a second frequency band different from the first frequency band received from the antenna substantially as a differential signal from the balanced output terminal, and a receiving circuit connected to the balanced output terminal and having a circuit in which a gain of a signal of a differential component is higher than that of a signal of an in-phase component, or a loss of the signal of the differential component is lower than that of the signal of the in-phase component.
    Type: Application
    Filed: December 17, 2003
    Publication date: September 16, 2004
    Inventors: Toshifumi Nakatani, Atsushi Yamamoto, Hisashi Adachi
  • Patent number: 6784817
    Abstract: In the prior art, it has been difficult to provide a data generator and a data generating method which serve to implement an efficient transmitter, as well as a transmitter utilizing this data generator. The present invention provides a raw data generator that generates, from an inputted signal, an I signal and a Q signal which are orthogonal to each other and an amplitude component of a quadrature signal composed of the I and Q signals, a delta sigma modulator that delta-sigma-modulates the amplitude component, a first multiplier that outputs first data obtained by multiplexing normalized I data obtained by dividing the I signal by the amplitude component, by the delta-sigma-modulated signal, and a second multiplier that outputs second data obtained by multiplexing normalized Q data obtained by dividing the Q signal by the amplitude component, by the delta-sigma-modulated signal.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Matsuura, Hisashi Adachi
  • Publication number: 20040140511
    Abstract: A semiconductor differential circuit comprising a semiconductor substrate, a first semiconductor device on the semiconductor substrate having a gate electrode for having one of differential signals conveyed thereto and a drain electrode for outputting one of the differential signals controlled by the gate electrode, a second semiconductor device formed on the semiconductor substrate having a gate electrode for having the other of the differential signals conveyed thereto and a drain electrode for outputting the other of the differential signals controlled by the gate electrode, and wherein the drain electrode and drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which the drain electrode is grounded via a predetermined resistance, and the drain electrode is grounded via the predetermined resistance.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 22, 2004
    Inventors: Toshifumi Nakatani, Hisashi Adachi, Yukio Hiraoka
  • Publication number: 20040136169
    Abstract: To provide a printed circuit board, a buildup substrate and a method of manufacturing the printed circuit board capable of curbing a transmission loss thereof at a desired frequency.
    Type: Application
    Filed: September 30, 2003
    Publication date: July 15, 2004
    Inventors: Shigeru Morimoto, Hisashi Adachi, Toshifumi Nakatani, Koji Takinami
  • Publication number: 20040128279
    Abstract: A data converter arranged to enable linear high-efficiency amplification of a signal having a fluctuating envelope. The data converter has a computation circuit, a vector quantizer, and an output terminal. The computation circuit is formed by connecting n (n: a natural number) number of unit circuits each including a vector subtracter having a first input terminal and a second input terminal, and a vector integrator connected to an output side of the vector subtracter. An output at the output terminal and/or an output from each vector integrator are input to the vector subtracter through the second input terminal in the corresponding unit circuit. The vector subtracter outputs data obtained by subtracting a vector input through the second input terminal from a vector input through the first input terminal. The vector quantizer outputs a predetermined value quantized at least with respect to the magnitude of the input vector.
    Type: Application
    Filed: October 10, 2003
    Publication date: July 1, 2004
    Inventors: Toru Matsuura, Hisashi Adachi
  • Publication number: 20040081266
    Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
    Type: Application
    Filed: December 8, 2003
    Publication date: April 29, 2004
    Inventors: Hisashi Adachi, Toshifumi Nakatani, Hiroaki Kosugi, Shunsuke Hirano, Masakatsu Maeda
  • Patent number: 6728526
    Abstract: A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5).
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: April 27, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryoichi Yamada, Shunsuke Hirano, Yasunori Miyahara, Hisashi Adachi, Hisashi Takahashi, Hiroki Kojima
  • Publication number: 20040075497
    Abstract: The conventional feedforward amplifier is unable to suppress distortion components efficiently. The present invention provides a feedforward amplifier wherein the vector adjustor is adjusted so that (1) suppression is performed on only the distortion component generated within a predetermined frequency range out of the range of frequencies to be suppressed in which distortion components to be suppressed occur or (2) the suppression of the distortion component generated within the predetermined frequency range is greater than the suppression of the distortion component generated within the frequency range other than the predetermined frequency range out of the range of frequencies to be suppressed, and the pre-distortion circuit is adjusted so that at least the distortion component generated within the frequency range other than the predetermined frequency range is suppressed.
    Type: Application
    Filed: November 6, 2003
    Publication date: April 22, 2004
    Inventors: Masayuki Miyaji, Kaoru Ishida, Toshimitsu Matsuyoshi, Hisashi Adachi, Seiji Fujiwara
  • Publication number: 20040066244
    Abstract: The present invention provides an oscillator or PLL circuit which can balance the characteristics of a circuit without being affected by noise from a signal line or a supply line. The present invention provides an oscillator comprising a resonance circuit has a first series connected circuit having coils and a power terminal, a second series connected circuit having capacitors and a varactor having directional characteristics, and a third series connected circuit having capacitors and a varactor having directional characteristics. The first, second, and third series connected circuits are connected in parallel. The varactors are connected so as to have opposite directionalities with respect to a connection side of the second and third series connected circuit. The capacities of the varactors are varied by external control. The varied capacities determine an oscillation frequency.
    Type: Application
    Filed: July 15, 2003
    Publication date: April 8, 2004
    Inventors: Koji Takinami, Hisashi Adachi
  • Patent number: 6717998
    Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: April 6, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Adachi, Toshifumi Nakatani, Hiroaki Kosugi, Masakatsu Maeda, Shunsuke Hirano
  • Publication number: 20040053644
    Abstract: A wireless communication base station system of the present invention includes a wireless key base station, an optical forward base station, and an optical transmitter which connects the wireless key base station and the optical forward base station to each other. An optical signal modulated by a signal component and that modulated by a distortion component are transmitted from the wireless key base station to the optical forward base station. In the optical forward base station, these optical signals are converted to high-frequency electrical signals, and the high-frequency signal consisting of the signal component is amplified. Thereafter, the amplified signal is combined with the high-frequency signal consisting of the distortion component with their phases opposite to each other, so that the distortion component include in the amplified signal is removed.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 18, 2004
    Inventors: Toshimitsu Matsuyoshi, Kaoru Ishida, Hisashi Adachi
  • Publication number: 20040036530
    Abstract: An amplifier circuit has: a delta-sigma modulator which delta-sigma modulates a signal; and an amplifier which is connected to an output of the delta-sigma modulator. Tn the amplifier circuit, an output voltage of the delta-sigma modulator is controlled in accordance with an output power of the amplifier. When the output power of the amplifier is reduced, the output voltage of the delta-sigma modulator is lowered.
    Type: Application
    Filed: May 12, 2003
    Publication date: February 26, 2004
    Inventors: Toru Matsuura, Hisashi Adachi
  • Publication number: 20040037369
    Abstract: In the prior art, it has been difficult to provide a data generator and a data generating method which serve to implement an efficient transmitter, as well as a transmitter utilizing this data generator. The present invention provides a raw data generator that generates, from an inputted signal, an I signal and a Q signal which are orthogonal to each other and an amplitude component of a quadrature signal composed of the I and Q signals, a delta sigma modulator that delta-sigma-modulates the amplitude component, a first multiplier that outputs first data obtained by multiplexing normalized I data obtained by dividing the I signal by the amplitude component, by the delta-sigma-modulated signal, and a second multiplier that outputs second data obtained by multiplexing normalized Q data obtained by dividing the Q signal by the amplitude component, by the delta-sigma-modulated signal.
    Type: Application
    Filed: June 11, 2003
    Publication date: February 26, 2004
    Inventors: Toru Matsuura, Hisashi Adachi
  • Publication number: 20040037571
    Abstract: Plural subcarrier-multiplexed AM signals 30 are input and narrow-band-FM-modulated by a voltage controlled oscillator 4 including the fundamental carrier wave and higher-order harmonics as the output, and the FM carrier wave component of the higher-order harmonics of the fundamental carrier wave is selectively taken out by a band-rejection filter 5, shifted to the lower frequency side by a frequency converter 7, converted into an optical signal by an electric/optic converter 3 and transmitted.
    Type: Application
    Filed: August 19, 2003
    Publication date: February 26, 2004
    Inventors: Masanori Iida, Hisashi Adachi, Hiroyuki Asakura
  • Publication number: 20040038648
    Abstract: A transmitting circuit device has a first signal source which outputs a first signal that is a binary or multilevel discrete analog signal or a discrete analog signal with a binary or multilevel envelope and that has signal components and quantization noise components; a second signal source which outputs a second signal composed of the quantization noise components; a first amplifier which amplifies the first signal; and a combiner which cancels out the quantization noise components by combining an output of the first amplifier and the second signal.
    Type: Application
    Filed: June 11, 2003
    Publication date: February 26, 2004
    Inventors: Toru Matsuura, Hisashi Adachi
  • Publication number: 20040014449
    Abstract: A radio interference suppression circuit used in a radio circuit of performing duplex transmission, comprises a first directional coupler of receiving a transmission frequency signal and then bifurcating and outputting the signal; and a second directional coupler which acquires, through one input thereof, a signal outputted from a reception filter of an antenna multiplexer and containing a reception frequency signal and the leakage signal component of a transmission frequency signal, and acquires, through the other input thereof, the transmission frequency signal outputted from one output of the first directional coupler, and which combines and outputs these acquired signals; wherein the leakage signal component of the transmission frequency signal contained in the signal inputted through the one input of the second directional coupler and the transmission frequency signal inputted through the other input of the second directional coupler are adjusted to be substantially of equal amplitude and reversed phase.
    Type: Application
    Filed: March 19, 2003
    Publication date: January 22, 2004
    Inventors: Hisashi Adachi, Kaoru Ishida, Makoto Sakakura