Patents by Inventor Hisashi Ohtani

Hisashi Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7943930
    Abstract: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani
  • Patent number: 7932589
    Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: April 26, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Takaaki Koen, Yuto Yakubo, Makoto Yanagisawa, Hisashi Ohtani, Eiji Sugiyama, Nozomi Horikoshi
  • Patent number: 7928438
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 7906847
    Abstract: To provide a semiconductor device which can increase reliability with respect to external force, especially pressing force, while the circuit size or the capacity of memory is maintained. A pair of structure bodies each having a stack of fibrous bodies of an organic compound or an inorganic compound, which includes a plurality of layers, especially three or more layers, is impregnated with an organic resin, and an element layer provided between the pair of structure bodies are included. The element layer and the structure body can be fixed to each other by heating and pressure bonding. Further, a layer for fixing the element layer and the structure body may be provided. Alternatively, the structure body fixed to an element layer can be formed in such a way that after a plurality of fibrous bodies is stacked over the element layer, the fibrous bodies are impregnated with an organic resin.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: March 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Eiji Sugiyama
  • Patent number: 7898166
    Abstract: It is an object of the invention to provide a light emitting device in which burden on a light emitting element having low luminous efficiency is relieved, and the deterioration of a light emitting element, the reduction in color reproduction due to the deteriorated light emitting element, and increase in electric power consumption can be suppressed. A light emitting device according to the invention has light emitting elements each of which emits one of colors corresponding to three primary colors. Further, one feature of the light emitting device according to the invention has a light emitting element which emits a neutral color. The light emitting device according to the invention has a structure in which a plurality of pixels having light emitting elements each of which emits one of colors corresponding to three primary colors, and a light emitting element which emits a neutral color as one group, are arranged.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 7898605
    Abstract: An conductive coating serves as a light shield film and is kept at a given voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 7892952
    Abstract: Provided are a laser apparatus of continuous oscillation that is capable of enhancing the efficiency of substrate processing, a laser irradiation method, and a manufacturing method for a semiconductor device using the laser apparatus. A portion of a semiconductor film that should be left on a substrate after patterning is grasped in accordance with a mask. Then, a portion to be scanned with a laser light is determined so that it is possible to crystallize at least the portion to be obtained through the patterning. Also, a beam spot is made to strike the portion to be scanned. As a result, the semiconductor film is partially crystallized. That is, with the present invention, the laser light is not scanned and irradiated onto the entire surface of a semiconductor film but is scanned so that at least an indispensable portion is crystallized.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: February 22, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Mai Akiba
  • Patent number: 7888702
    Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: February 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Hisashi Ohtani, Misako Hirosue
  • Publication number: 20110024853
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.
    Type: Application
    Filed: September 29, 2010
    Publication date: February 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Eiji SUGIYAMA, Yoshitaka DOZEN, Hisashi OHTANI, Takuya TSURUME
  • Patent number: 7863622
    Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: January 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20100321420
    Abstract: The invention provides a light emitting device which can suppress the reduction of luminance in accordance with the light emission time and light emission at a high luminance. Moreover, the invention relates to a driving method which can suppress the reduction of luminance in accordance with the light emission time and light emission at a high luminance. The light emitting device of the invention can display a plurality of colors of which brightness and chromaticity are different by visually mixing light emission of a plurality of light emitting elements of which light emission colors are different. When a visually mixed display color is formed, a white light emission is exhibited.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 23, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Yoshifumi Tanada, Aya Anzai
  • Patent number: 7847294
    Abstract: There is provided a method in which a TFT with superior electrical characteristics is manufactured and a high performance semiconductor device is realized by assembling a circuit with the TFT. The method of manufacturing the semiconductor device includes: a step of forming a crystal-containing semiconductor film by carrying out a thermal annealing to a semiconductor film; a step of carrying out an oxidizing treatment to the crystal-containing semiconductor film; a step of carrying out a laser annealing treatment to the crystal-containing semiconductor film after the oxidizing treatment has been carried out; and a step of carrying out a furnace annealing treatment to the crystal-containing semiconductor film after the laser annealing. The laser annealing treatment is carried out with an energy density of 250 to 5000 mJ/cm2.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: December 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Tamae Takano, Shunpei Yamazaki
  • Publication number: 20100295046
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Toru MITSUKI, Akiharu MIYANAGA, Yasushi OGATA
  • Patent number: 7837792
    Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that accelerates the crystallization of silicon, an adverse influence of this metal element can be suppressed. A semiconductor device manufacturing method is comprised of the steps of: forming an amorphous silicon film on a substrate having an insulating surface; patterning the amorphous silicon film to form a predetermined pattern; holding a metal element that accelerates the crystallization of silicon in such a manner that the metal element is brought into contact with the amorphous silicon film; performing a heating process to crystalize the amorphous silicon film, thereby being converted into a crystalline silicon film; and etching a peripheral portion of the pattern of the crystalline silicon film.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: November 23, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto, Shunpei Yamazaki
  • Patent number: 7817170
    Abstract: The invention provides a driving method of a semiconductor display device in which generation of a pseudo contour can be suppressed while the operating frequency of a driver circuit is suppressed. Furthermore, the invention provides a driving method of a semiconductor display device in which generation of a pseudo contour can be suppressed while the decrease in image quality is suppressed. In a semiconductor display device including a plurality of pixels, tables each storing data for determining a subframe period for light emission among a plurality of subframe periods are provided for a plurality of arbitrary pixels among the plurality of pixels respectively. The table is stored in a memory.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: October 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keisuke Miyagawa, Shou Nagao, Hisashi Ohtani
  • Patent number: 7808098
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 5, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eiji Sugiyama, Yoshitaka Dozen, Hisashi Ohtani, Takuya Tsurume
  • Patent number: 7791571
    Abstract: The invention provides a light emitting device which can suppress the reduction of luminance in accordance with the light emission time and light emission at a high luminance. Moreover, the invention relates to a driving method which can suppress the reduction of luminance in accordance with the light emission time and light emission at a high luminance. The light emitting device of the invention can display a plurality of colors of which brightness and chromaticity are different by visually mixing light emission of a plurality of light emitting elements of which light emission colors are different. When a visually mixed display color is formed, a white light emission is exhibited.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: September 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yoshifumi Tanada, Aya Anzai
  • Patent number: RE42097
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: RE42139
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: RE42241
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani