Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Abstract: An apparatus and method for forming a three-dimensional (3D) pattern using electrojetting, the apparatus including: a syringe tip having one end from which a polymer jet is discharged; a substrate that is disposed in a direction in which the polymer jet is discharged, and that forms an electric field between the substrate and the syringe tip; and a movement unit that moves the syringe tip or the substrate, wherein the polymer jet discharged from the syringe tip is moved relative to an upper side of the substrate and is stacked on the substrate.

Abstract: Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Abstract: A composition for cleaning a magnetic pattern, a method of manufacturing a magnetic memory device, a method of forming a magnetic pattern, and a magnetic memory device, the composition including a glycol ether-based organic solvent; a decomposing agent that includes an aliphatic amine; and at least one of a chelating agent, or a cleaning accelerator that includes an organic alkaline compound, wherein the composition is devoid of water.

Abstract: The present invention provides a method for synthesizing a Bi2TeySe3-y thermoelectric nanocompound (0<y<3), comprising the following steps: preparing a Bi—Te—Se solution by adding Bi, Te, and Se precursors to a solvent (step 1); preparing a hydrate by mixing the Bi—Te—Se solution prepared in step 1) with a base aqueous solution (step 2); preparing a Bi2TeySe3-y reactant by liquid phase reduction at room temperature after adding a reducing agent to the hydrate prepared in step 2) (step 3); aging the Bi2TeySe3-y reactant prepared in step 3) (step 4); and preparing Bi2TeySe3-y nanoparticles by filtering and drying the Bi2TeySe3-y reactant aged in step 4) (step 5). The Bi2TeySe3-y thermoelectric nanocompound synthesized by the method of the present invention via liquid phase reduction is composed of regular nanoparticles since the method does not need any additional heat-treatment to eliminate chemical additives and prevents particles from being over-grown.

Abstract: The present invention provides a method for synthesizing a BixSb2-xTe3 thermoelectric nanocompound (0<x<2), comprising the following steps: preparing a Bi—Sb—Te solution by adding Bi, Sb, and Te precursors to a solvent (step 1); preparing a Bi—Sb—Te hydrate by mixing the Bi—Sb—Te solution prepared in step 1) with a base aqueous solution (step 2); preparing a BixSb2-xTe3 reactant by liquid phase reduction at room temperature after adding a reducing agent to the Bi—Sb—Te hydrate prepared in step 2) (step 3); aging the BixSb2-xTe3 reactant prepared in step 3) (step 4); and preparing BixSb2-xTe3 nanoparticles by filtering and drying the BixSb2-xTe3 reactant aged in step 4) (step 5). The BixSb2-xTe3 thermoelectric nanocompound synthesized by the method of the present invention via liquid phase reduction is composed of regular nanoparticles since the method does not need any additional heat-treatment to eliminate chemical additives and prevents particles from being over-grown.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.

Abstract: A method of forming a plug and manufacturing a semiconductor device, a polishing chamber, and a semiconductor device, the method of forming a plug including forming an opening in an insulating interlayer pattern on a substrate; forming a metal layer to fill the opening; performing a first CMP process during a first time period until a top surface of the insulating interlayer pattern is exposed while pressing the substrate onto a first polishing pad to polish the metal layer; performing a second CMP process during a second time period while pressing the substrate onto a second polishing pad to polish the metal layer and the insulating interlayer pattern, so that a metal plug is formed in the insulating interlayer pattern; and performing a first cleaning process on the second polishing pad while keeping the substrate spaced apart from the second polishing pad on the second platen.

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Abstract: A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.

Abstract: A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.

Abstract: In a method of manufacturing an integrated circuit (IC) device, a photomask is wet-processed using a cleaning composition comprising an organic acid, an oxidizing agent, and deionized water (DIW).

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A display apparatus includes a display panel, a backlight unit, a backlight control circuit, sensors, a read-out circuit and a sensor auxiliary circuit. The display panel includes pixels and displays an image. The backlight unit includes a first light source which emits a first light in a infrared light range. The backlight control circuit controls a brightness of the first light source. The sensors sense an external signal and outputs first sensing signals. The read-out circuit outputs the first sensing signals as second sensing signals. The sensor auxiliary circuit compares a maximum value and a minimum value of the second sensing signals and provides a brightness control signal to the backlight control circuit based on the compared difference to control the brightness of the first light source.

Abstract: Disclosed is a structure having a superhydrophobic and amphiphilic (oleophilic) surface and a fabrication method thereof. A polymer surface body disclosed herein may include high aspect ratio nanostructures on a surface thereof, wherein an aspect ration of the high aspect ratio nanostructure is 1 to 100, and may include a hydrophobic thin film on the high aspect ratio nanostructure. A method of fabricating a polymer surface body disclosed herein may include performing a surface modification treatment on a polymer to form a high aspect ratio nanostructure having an aspect ration of 1 to 100, and forming a hydrophobic thin film on a surface containing the nanostructures.