Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

Abstract: An oil-collecting apparatus includes: a body including an inlet through which a liquid is introduced, a first outlet through which purified water generated from the liquid introduced through the inlet is discharged, and a second outlet through which materials collected from the liquid are discharged; and a filter arranged at the first outlet of the body and generating the purified water by collecting the materials included in the liquid by allowing the liquid introduced through the inlet to pass therethrough.

Abstract: An etching composition selectively removes a titanium nitride film from a stacked conductive film structure including a titanium nitride (TiN) film and a tantalum nitride (TaN) film. The etching composition configured to etch titanium nitride (TiN) includes 5 wt % to 30 wt % of hydrogen peroxide, 15 wt % to 50 wt % of acid compound, and 0.001 wt % to 5 wt % of corrosion inhibitor, with respect to a total weight of the etching composition, wherein the acid compound includes at least one of phosphoric acid (H3PO4), nitric acid (HNO3), hydrochloric acid (HCl), hydroiodic acid (HI), hydrobromic acid (HBr), perchloric acid (HNO4), silicic acid (H2SiO3), boric acid (H3BO3), acetic acid (CH3COOH), propionic acid (C2H5COOH), lactic acid (CH3CH(OH)COOH), and glycolic acid (HOCH2COOH).

Abstract: A method for manufacturing a conductive film, the method comprising the steps of: preparing a mixture liquid in which a catalytic metal is dispersed in a precursor or a precursor compound of a two-dimensional nanomaterial; and forming a catalytic metal/two-dimensional nanomaterial by irradiating the mixture liquid with ultrasonic waves to generate microbubbles, degrading the precursor compound using energy, which is generated when the microbubbles burst, to synthesize the two-dimensional nanomaterial on an outer wall of the catalytic metal, wherein the method further comprises: dispersing the catalytic metal/two-dimensional nanomaterial in a dispersion to prepare ink; and applying the ink on a substrate and performing rapid air-sintering. Thus, the two-dimensional nanomaterial is synthesized on an outer wall of a non-noble metal having high oxidative characteristics, thereby preventing oxidation of the metal from air and increasing thermal conductivity and electrical conductivity.

Abstract: Provided are a texture compressing method and a texture compressing apparatus, which compress some color information of a texture block, which is unable to realize all colors included in the texture block by a determined compression bit number, to be stored in a compression data bit of a texture block, which is able to realize all colors included in the texture block by a bit number lower than the determined compression bit number, based on a color distribution of each texture block, and a texture decompressing method and a texture decompressing apparatus corresponding to the texture compressing method and the texture compressing apparatus.

Abstract: Provided are a method of generating a functional coverage model from a hardware description language (HDL) code for a circuit design and performing verification of the circuit design by using the functional coverage model, and a computing system in which the method is performed.

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Abstract: An apparatus and method for forming a three-dimensional (3D) pattern using electrojetting, the apparatus including: a syringe tip having one end from which a polymer jet is discharged; a substrate that is disposed in a direction in which the polymer jet is discharged, and that forms an electric field between the substrate and the syringe tip; and a movement unit that moves the syringe tip or the substrate, wherein the polymer jet discharged from the syringe tip is moved relative to an upper side of the substrate and is stacked on the substrate.

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Abstract: Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Abstract: A composition for cleaning a magnetic pattern, a method of manufacturing a magnetic memory device, a method of forming a magnetic pattern, and a magnetic memory device, the composition including a glycol ether-based organic solvent; a decomposing agent that includes an aliphatic amine; and at least one of a chelating agent, or a cleaning accelerator that includes an organic alkaline compound, wherein the composition is devoid of water.

Abstract: The present invention provides a method for synthesizing a Bi2TeySe3-y thermoelectric nanocompound (0<y<3), comprising the following steps: preparing a Bi—Te—Se solution by adding Bi, Te, and Se precursors to a solvent (step 1); preparing a hydrate by mixing the Bi—Te—Se solution prepared in step 1) with a base aqueous solution (step 2); preparing a Bi2TeySe3-y reactant by liquid phase reduction at room temperature after adding a reducing agent to the hydrate prepared in step 2) (step 3); aging the Bi2TeySe3-y reactant prepared in step 3) (step 4); and preparing Bi2TeySe3-y nanoparticles by filtering and drying the Bi2TeySe3-y reactant aged in step 4) (step 5). The Bi2TeySe3-y thermoelectric nanocompound synthesized by the method of the present invention via liquid phase reduction is composed of regular nanoparticles since the method does not need any additional heat-treatment to eliminate chemical additives and prevents particles from being over-grown.

Abstract: The present invention provides a method for synthesizing a BixSb2-xTe3 thermoelectric nanocompound (0<x<2), comprising the following steps: preparing a Bi—Sb—Te solution by adding Bi, Sb, and Te precursors to a solvent (step 1); preparing a Bi—Sb—Te hydrate by mixing the Bi—Sb—Te solution prepared in step 1) with a base aqueous solution (step 2); preparing a BixSb2-xTe3 reactant by liquid phase reduction at room temperature after adding a reducing agent to the Bi—Sb—Te hydrate prepared in step 2) (step 3); aging the BixSb2-xTe3 reactant prepared in step 3) (step 4); and preparing BixSb2-xTe3 nanoparticles by filtering and drying the BixSb2-xTe3 reactant aged in step 4) (step 5). The BixSb2-xTe3 thermoelectric nanocompound synthesized by the method of the present invention via liquid phase reduction is composed of regular nanoparticles since the method does not need any additional heat-treatment to eliminate chemical additives and prevents particles from being over-grown.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.