Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

Abstract: The present invention relates to a novel crystalline form of 5-chloro-N-({(5S)-2-oxo-3-[4-(5,6-dihydro-4H-[1,2,4]triazin-1-yl)phenyl]-1,3-oxazolidin-5-yl}methyl)thiophene-2-carboxamide methanesulfonate and a pharmaceutical composition containing the same. The novel crystalline form of a compound according to the present invention exhibits excellent stability even in high-temperature and humidity environments, and thus can be favorably used to prevent or treat diseases, such as thrombosis, myocardial infarction, atherosclerosis, inflammation, stroke, angina pectoris, restenosis after angioplasty, and thromboembolism.

Abstract: Provided are a light source package and a display device including the light source package. The light source package includes a substrate; a light-emitting device mounted on the substrate; a red phosphor layer formed adjacent to a surface of the light-emitting device; and an encapsulation layer for encapsulating the light-emitting device and the red phosphor layer, wherein a phosphor of the red phosphor layer is a fluoride-based red phosphor or a sulfide-based red phosphor. The light source package and the display device including the light source package display excellent color reproduction, without discoloration due to moisture after a long period of time.

Abstract: A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Abstract: Provided are methods of use of compounds comprising a self-immolative group, which compounds may include a protein (for example, an oligopeptide, a polypeptide, an antibody, or the like) having substrate-specificity for a target and an active agent (for example, a drug, a toxin, a ligand, a detection probe, or the like) having a specific function or activity.

Abstract: In some aspects, the invention relates to an antibody-drug conjugate, comprising an anti-CD19 antibody; a linker; and an active agent. The antibody-drug conjugate may comprise a self-immolative group. The linker may comprise an O-substituted oxime, e.g., wherein the oxygen atom of the oxime is substituted with a group that covalently links the oxime to the active agent; and the carbon atom of the oxime is substituted with a group that covalently links the oxime to the antibody.

Abstract: In some aspects, the invention relates to an antibody-drug conjugate, comprising an anti-epidermal growth factor receptor (“EGFR”) antibody; a linker; and an active agent. The antibody-drug conjugate may comprise a self-immolative group. The linker may comprise an O-substituted oxime, e.g., wherein the oxygen atom of the oxime is substituted with a group that covalently links the oxime to the drug; and the carbon atom of the oxime is substituted with a group that covalently links the oxime to the antibody.

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

Abstract: Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.

Abstract: A semiconductor LED package includes a package body having first and second electrode structures and an LED chip connected to at least one of the first and second electrode structures using a wire. The LED chip includes a light emitting structure and first and second electrode parts. At least one of the first and second electrode parts includes a bonding electrode layer made of a material having the same composition as a material of the wire and bonded to the wire, and an uneven electrode layer disposed on the bonding electrode layer and having at least one through hole filled with the wire. The at least one through hole allows a top surface of the bonding electrode layer to be exposed therebelow.

Abstract: A semiconductor light emitting device includes a wiring board including a mounting surface on which a first wiring electrode and a second wiring electrode are disposed; a semiconductor light emitting diode (LED) chip including a first surface on which a first electrode and a second electrode are disposed, the first surface facing the mounting surface, the semiconductor LED chip further including a second surface positioned opposite to the first surface, and side surfaces positioned between the first and second surfaces, the first and second electrodes being connected to the first and second wiring electrodes, respectively; and a reflective layer disposed on at least one of the second surface and the side surfaces of the semiconductor LED chip.

Abstract: A method and apparatus for separating real DVC via defects from nuisance based on Net Tracing Classification of eBeam VC die comparison inspection results are provided. Embodiments include performing an eBeam VC die comparison inspection on each via of a plurality of dies; determining DVC vias based on the comparison; performing a Net Tracing Classification on the DVC vias; determining S/D DVC vias based on the Net Tracing Classification; and performing a die repeater analysis on the S/D DVC vias to determine systematic design-related DVC via defects.

Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

Abstract: Provided are compounds comprising a self-immolative group, and the compounds comprising a self-immolative group according to the present invention may include a protein (for example, an oligopeptide, a polypeptide, an antibody, or the like) having substrate-specificity for a target and an active agent (for example, a drug, a toxin, a ligand, a detection probe, or the like) having a specific function or activity.

Abstract: The present invention relates to a method and an apparatus for allocating an Internet Protocol (IP) address by a direct communication terminal which selects a first local IP address that is a local IP address of a first terminal, transmits an IP address verification request message including the first local IP address to a second terminal, receives an IP address verification response message including information on duplication of the first local IP address, and determines whether to use the first local IP address based on the IP address verification response message.