Abstract: Provided is an integrated circuit. The integrated circuit includes: a first standard cell comprising a P-type Fin Field Effect Transistor (FinFET) region and an N-type FinFET region; and a filler cell adjacent to the first standard cell in a first direction and including a first region and a second region arranged in a second direction perpendicular to the first direction, wherein the first region includes a plurality of first insulating structures spaced apart from each other in the first direction, and the second region includes a second insulating structure having a width greater than that of at least one of the plurality of first insulating structures in the first direction, and one of the first region and the second region is arranged adjacent to the P-type FinFET region in the first direction and the other is arranged adjacent to the N-type FinFET region in the first direction.

Abstract: A semiconductor device is provided. A semiconductor device includes a filler cell including first and second insulating structures, the first and second insulating structures extending in a first direction, the filler cell being defined by first cell boundaries; and a neighboring cell including a third insulating structure, the third insulating structure extending in the first direction, the neighboring cell being adjacent to the filler cell in the first direction and defined by second cell boundaries, wherein the first and second insulating structures are spaced apart from one another in a second direction, is the second direction being perpendicular to the first direction.

Abstract: Provided is an integrated circuit. The integrated circuit includes: a first standard cell comprising a P-type Fin Field Effect Transistor (FinFET) region and an N-type FinFET region; and a filler cell adjacent to the first standard cell in a first direction and including a first region and a second region arranged in a second direction perpendicular to the first direction, wherein the first region includes a plurality of first insulating structures spaced apart from each other in the first direction, and the second region includes a second insulating structure having a width greater than that of at least one of the plurality of first insulating structures in the first direction, and one of the first region and the second region is arranged adjacent to the P-type FinFET region in the first direction and the other is arranged adjacent to the N-type FinFET region in the first direction.

Abstract: A semiconductor device is provided. A semiconductor device includes a filler cell including first and second insulating structures, the first and second insulating structures extending in a first direction, the filler cell being defined by first cell boundaries; and a neighboring cell including a third insulating structure, the third insulating structure extending in the first direction, the neighboring cell being adjacent to the filler cell in the first direction and defined by second cell boundaries, wherein the first and second insulating structures are spaced apart from one another in a second direction, is the second direction being perpendicular to the first direction.

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

Abstract: A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.

Abstract: An adaptive body bias (ABB) circuit and a semiconductor integrated circuit (IC) having the ABB circuit include: a logic circuit performing logic calculations, a clock line through which a clock signal is transmitted to the logic circuit, and at least one bias line through which a bias voltage is applied to the logic circuit, wherein the bias voltage is applied to a body of a metal oxide semiconductor (MOS) transistor constituting the logic circuit, and the bias line is arranged at a predetermined distance from the clock line to shield the clock signal from crosstalk due to other adjacent signal lines.

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

Abstract: A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.

Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.

Abstract: A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.

Abstract: A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.

Abstract: A multi-core processor includes first processor core including a first instruction fetch unit and out-of-order execution data units, a second processor core including a second instruction fetch unit and in-order execution data units, and a shared-level 1 cache including a level 1-instruction cache shared between the first instruction fetch unit and the second instruction fetch unit and a level 1-data cache shared between the out-of-order execution data units and the in-order execution data.

Abstract: A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock signal generator configured to receive the common clock signal, the first clock signal generator having a first clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data; and a second clock signal generator configured to receive the common clock signal, the second clock signal generator having a second clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data.

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.