Abstract: Circuits and methods for driving buses (data buses or address buses) which provide a reduction in interference such as crosstalk between adjacent bus lines of a bus, even as the width of the bus increases and the intervals between the bus lines decrease. In the bus driving circuits and methods, a portion of the bus lines are driven at a first time, and a portion of the bus lines are driven at a second time, subsequent to the first time, so as to reduce or eliminate crosstalk between adjacent bus lines.

Abstract: A method of HDL simulation is described, which may enhance HDL simulation accuracy by allowing a simulator to process a negative setup time and/or hold time. For an electronic circuit device negative setup time and/or a negative hold time, a simulation may be executed without altering the negative setup time and/or hold time to be interpreted as zero. A setup time and/or hold time may be negative relative to a particular clock cycle while being positive relative to another clock cycle. Incorporating the value of the negative setup time and/or hold time without altering its value to zero may increase the accuracy of HDL simulations.

Abstract: Information designated as a hot routine by an application program is stored in a hot routine memory of the microprocessor system. A processor requests information, and a controller controls the hot routine memory to output information requested by a processor when the hot routine memory stores the requested information. The controller includes address translation information to translate the address used in the request from the processor to an address of the information in the hot routine memory.

Abstract: A clock tree synthesis (CTS) apparatus, generator, and method for synthesizing a clock tree includes a plurality of clock signal generators that output different clock signals generated from a reference clock signal. The clock signal generators includes an additional logic circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized. In one example, the clock signal generator is a flip-flop and the additional logic circuit is a tri-state buffer.

Abstract: A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning test circuit may also include a plurality of pads. Each pad may be arranged between a pair of circuit groups so that at least one output terminal of a unit delay circuit of one of the plurality of circuit groups is connected to one of the pads. The speed binning test device performs a speed binning test method in which a signal through the circuit groups is delayed, and on-chip-variations are monitored to determine a total signal delay time through the chain structure.

Abstract: A memory controller increases the effective bus bandwidth of a computer system. The memory controller includes a first port and a second port which receive and transmit N-bit data values, respectively; a third port receiving and transmitting 2N-bit data values; and a fourth port and a fifth port receiving and transmitting the N-bit data values, respectively. Here, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and a memory device corresponding to the second port in response to a command signal and an address input via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port.

Abstract: In a bus arbitration method and bus arbiter which simultaneously considers fairness and priority and enables fairness and priority to be readjusted by a program, that is, by software, arbitration for ownership of a bus connected to a plurality of bus masters comprises grouping the plurality of bus masters into a plurality of groups and arbitrating the frequency of each bus master's ownership of the bus according to the result of the grouping. It is preferable that each of the plurality of groups has a priority different from the priorities of the others, and in arbitrating the frequency of each bus master owning the bus, arbitration of ownership of the bus by bus masters belonging to the same group is performed according to a round-robin method.

Abstract: Circuits and methods for driving buses (data buses or address buses) which provide a reduction in interference such as crosstalk between adjacent bus lines of a bus, even as the width of the bus increases and the intervals between the bus lines decrease. In the bus driving circuits and methods, a portion of the bus lines are driven at a first time, and a portion of the bus lines are driven at a second time, subsequent to the first time, so as to reduce or eliminate crosstalk between adjacent bus lines.

Abstract: In methods for compressing data, when differences between two adjacent data among a series of N data , where N is a positive integer, are all less than a reference value, delta data values are generated on the basis of the differences. When the differences are the reference value or less and at least one delta data is stored, a command indicating that compression operations are performed on the basis of the differences, the number of the stored delta data, and the stored delta data are generated as compressed data. The compression method of the present method can obtain higher compression efficiency as compared with conventional RLC or modified-RLC compression methods.

Abstract: An arithmetic device having a cache for performing arithmetic operations is provided. The cache stores previously performed resultant data and operand for an arithmetic operation and upon receiving a same operand to be operated upon, the corresponding stored resultant data is output, bypassing the arithmetic processing and operation by the processor. The device having the cache is also configured for outputting a partial resultant output for a partially matched operand.

Abstract: An arithmetic device having a cache for performing arithmetic operations is provided. The cache stores previously performed resultant data and operand for an arithmetic operation and upon receiving a same operand to be operated upon, the corresponding stored resultant data is output, bypassing the arithmetic processing and operation by the processor. The device having the cache is also configured for outputting a partial resultant output for a partially matched operand.

Abstract: A branch predictor generates an index to access a branch prediction table storing branch prediction reference data therein, considering a branch history, a branch instruction address, and a process ID. Accordingly, although context switching frequently occurs and a plurality of processes are under operation simultaneously in single microprocessor, the branch predictor has a high hit ratio of branch prediction. From the standpoint of an operating system of a computer system, the hit ratio is enhanced to reduce a stall phenomenon in the pipeline. As a result, program execution time can be shortened.