Abstract: A semiconductor test apparatus for determining memory failure, including a first at least one multiplexer. The first at least one multiplexer may include a first transistor and a second transistor, the first transistor and the second transistor being different sizes. The semiconductor may include a scan cell, the scan cell including a second at least one multiplexer. The second at least one multiplexer may include a third transistor and a fourth transistor, the third transistor and the fourth transistor being different sizes. Another semiconductor test apparatus including a plurality of scan cells and a plurality of multiplexers, each of the plurality of scan cells and the plurality of multiplexers formed in a single wrapper.

Abstract: A silicon on chip (SOC), may include function blocks, and a scan chain in each of the function blocks, the scan chains being adapted to conduct scan test operations in sync with a respective one of a plurality of clock signals having a different phase relative to each other, wherein during an isolation mode, the scan chains test combination circuits of the function blocks, and during an interface mode, the scan chains of adjacent ones of the function blocks test combination circuits between the adjacent ones of the function blocks.

Abstract: Information designated as a hot routine by an application program is stored in a hot routine memory of the microprocessor system. A processor requests information, and a controller controls the hot routine memory to output information requested by a processor when the hot routine memory stores the requested information. The controller includes address translation information to translate the address used in the request from the processor to an address of the information in the hot routine memory.

Abstract: A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.

Abstract: A semiconductor chip may include an internal circuit, at least one power gating transistor, a system manager, and/or at least one current regulator. The at least one power gating transistor may be configured to switch a supply of at least one drive voltage into the internal circuit. The system manager may be configured to generate a control signal corresponding to an activation state of the internal circuit. At least one current regulator may be configured to control an amount of a current flowing through the at least one power gating transistor in response to the control signal.

Abstract: An integrated circuit includes first and second power domains, a power supply control unit, and a switch block. The power supply control unit supplies a first voltage to the first power domain and a second voltage to the second power domain. The switch block provides at least one current path between the first and second power domains during a predetermined operating mode such as by connecting a first power line of the first power domain to a second power line of the second power domain.

Abstract: A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning test circuit may also include a plurality of pads. Each pad may be arranged between a pair of circuit groups so that at least one output terminal of a unit delay circuit of one of the plurality of circuit groups is connected to one of the pads. The speed binning test device performs a speed binning test method in which a signal through the circuit groups is delayed, and on-chip-variations are monitored to determine a total signal delay time through the chain structure.

Abstract: A clock tree synthesis (CTS) apparatus, generator, and method for synthesizing a clock tree includes a plurality of clock signal generators that output different clock signals generated from a reference clock signal. The clock signal generators includes an additional logic circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized. In one example, the clock signal generator is a flip-flop and the additional logic circuit is a tri-state buffer.

Abstract: A method of HDL simulation is described, which may enhance HDL simulation accuracy by allowing a simulator to process a negative setup time and/or hold time. For an electronic circuit device negative setup time and/or a negative hold time, a simulation may be executed without altering the negative setup time and/or hold time to be interpreted as zero. A setup time and/or hold time may be negative relative to a particular clock cycle while being positive relative to another clock cycle. Incorporating the value of the negative setup time and/or hold time without altering its value to zero may increase the accuracy of HDL simulations.

Abstract: In a bus arbitration method and bus arbiter which simultaneously considers fairness and priority and enables fairness and priority to be readjusted by a program, that is, by software, arbitration for ownership of a bus connected to a plurality of bus masters comprises grouping the plurality of bus masters into a plurality of groups and arbitrating the frequency of each bus master's ownership of the bus according to the result of the grouping. It is preferable that each of the plurality of groups has a priority different from the priorities of the others, and in arbitrating the frequency of each bus master owning the bus, arbitration of ownership of the bus by bus masters belonging to the same group is performed according to a round-robin method.

Abstract: For a processor having a plurality of sequential stages, variable (or idiosyncratic) wake-up latencies and a method for managing power in such a processor are provided. Each sequential stage includes one or more logic blocks and one or more power switches. A power controller can measure wake-up latencies for the logic blocks and control the power switches of the logic blocks by referring to the measured wake-up latencies, respectively.

Abstract: A processor with cache way prediction and method thereof. The processor includes a cache way prediction unit for predicting at least one cache way for selection from a plurality of cache ways. The processor may further include an instruction cache for accessing the selected at least one cache way, where the selected at least one cache way is less than all of the plurality of cache ways. The method includes predicting less than all of a plurality of cache ways for selection and accessing the selected less than all of the plurality of cache ways. In both the process and method thereof, by accessing less than all of the plurality of cache ways, a power consumption and delay may be reduced.

Abstract: In methods for compressing data, when differences between two adjacent data among a series of N data, where N is a positive integer, are all less than a reference value, delta data values are generated on the basis of the differences. When the differences are the reference value or less and at least one delta data is stored, a command indicating that compression operations are performed on the basis of the differences, the number of the stored delta data, and the stored delta data are generated as compressed data. The compression method of the present method can obtain higher compression efficiency as compared with conventional RLC or modified-RLC compression methods.

Abstract: A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.

Abstract: A memory controller increases the effective bus bandwidth of a computer system. The memory controller includes a first port and a second port which receive and transmit N-bit data values, respectively; a third port receiving and transmitting 2N-bit data values; and a fourth port and a fifth port receiving and transmitting the N-bit data values, respectively. Here, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and a memory device corresponding to the second port in response to a command signal and an address input via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port.

Abstract: A memory controller increases the effective bus bandwidth of a computer system. The memory controller includes a first port and a second port which receive and transmit N-bit data values, respectively; a third port receiving and transmitting 2N-bit data values; and a fourth port and a fifth port receiving and transmitting the N-bit data values, respectively. Here, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and a memory device corresponding to the second port in response to a command signal and an address input via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port.

Abstract: A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, and a fail detector for determining memory failure. Another semiconductor device for testing at least one of a plurality of memory devices, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, a reference data generator for generating reference data, and a fail detector for determining memory failure.

Abstract: A semiconductor test apparatus for determining memory failure, including a first at least one multiplexer. The first at least one multiplexer may include a first transistor and a second transistor, the first transistor and the second transistor being different sizes. The semiconductor may include a scan cell, the scan cell including a second at least one multiplexer. The second at least one multiplexer may include a third transistor and a fourth transistor, the third transistor and the fourth transistor being different sizes. Another semiconductor test apparatus including a plurality of scan cells and a plurality of multiplexers, each of the plurality of scan cells and the plurality of multiplexers formed in a single wrapper.

Abstract: A scan test method, device, and system may be provided to detect faults in embedded memories. The device may include a first select unit which may selectively output data inputs and may detect the faults in the embedded memories in response to a select signal S, a second select unit which may selectively output a data input from the first select unit and/or a scan input from an input terminal in response to a scan enable signal SE, and a flip-flop which may output data output from the second select unit to an output terminal in response to a clock signal CK.

Abstract: A branch predictor generates an index to access a branch prediction table storing branch prediction reference data therein. The index is generated in response to a combination of a branch history, a branch instruction address, and a process ID. The process ID is derived from one of multiple processes operating on a multi-processing computer with which the branch predictor is associated.