Abstract: A data carrier having a non-volatile electronic memory for holding large volumes of data and a microcontroller suitable for performing cryptographic operations. Access to the memory is possible only via the microcontroller. The data carrier is characterized in that, before data are stored in the memory, the user is authenticated for a data source using the microcontroller.

Abstract: An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is provided. A connection supplying the clock signal is connected to the clock input of the respective circuit units via respective controllable switching devices. The control inputs of the switching devices are connected to an output of a random signal generator, so that a circuit unit is operated in parallel or in series with one or more of the other circuit units on the basis of the random signal. A method of operating an integrated semiconductor circuit is also provided.

Abstract: Key management device for electronic memories and a method for the encrypted storage of digital data words in electronic memories, in which each stored data word is encrypted with a digital keyword, which may be different from another digital keyword of another stored data word.

Abstract: A method for determining a physical address from a virtual address, wherein a mapping regulation between the virtual address and the physical address is implemented as hierarchical tree structure with compressed nodes. First, a compression indicator included in the mapping regulation is read, and a portion of the virtual address associated with the considered node level is read. Using the compression indicator and the portion of the virtual address, an entry in the node list of the considered node is determined. The determined entry is read, whereupon the physical address can be determined directly, if the considered node level has been the hierarchically lowest node level. If higher node levels to be processed are present, the previous steps in determining the physical address for compressed nodes of lower hierarchy level are repeated until the hierarchically lowest node level is reached.

Abstract: A data processing device having a bus system, encryption devices for encrypting and decrypting information transmitted on the bus system, and at least one key change device for exchanging a key used. The keys used are changed automatically at irregular time intervals, which are preferably defined by a random number with the aid of an automatic state machine.

Abstract: Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

Abstract: In a method of storing a quantity of data in a target memory location, the data quantity is stored first in a non-volatile buffer memory location. It is then examined whether the data are successfully stored in the non-volatile buffer memory location. If the step of examining produces a positive result, the target memory location to which the predetermined quantity of data is to be written is cleared. After the step of clearing of the target memory location, the data are transferred from the non-volatile buffer memory location to the target memory location. To conclude the storage cycle, the non-volatile buffer memory location is then cleared so as to be available for a new storage operation. The effect achieved thereby is a secure and uncomplicated transfer of information from a source memory to the target memory.

Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

Abstract: An integrated circuit having at least one line pair to which a dual-rail signal is applied, a switching device, which is connected to the at least one line pair, is controlled by a signal applied to a control connection and is used to transmit the dual-rail signal, which has been applied to the line pair, to an additional line pair, and a memory cell, which is connected to the additional line pair and to a supply potential connection via a controllable switch.

Abstract: A selection transistor for a group of memory cells, preferably composed of 16-32 memory cells, is respectively introduced into the feed lines to the memory cells The selection transistor is opened to a line group for reading, while the control gates of all lines are low potential, and the current for each reading column leading through said line group is measured and stored. In a second step, the control gate of the line to be read is brought to a higher reading potential and the resulting current is compared to the previous current.

Abstract: In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus.

Abstract: In a method for modular multiplication of a multiplicand by a multiplier using a modulus, 1 multiplication shift values are initially determined by means of a multiplication-lookahead method while taking into account 1 blocks of consecutive digits of the multiplier. Subsequently, 1 reduction shift values are determined by means of a reduction-lookahead method for the 1 blocks of digits of the multiplier. The 1 multiplication shift values and the 1 reduction shift values are applied to an intermediate result from a previous iteration step, to the modulus or to a value derived from the modulus, and to the multiplicand, so as to obtain the 21+1 operands. By means of a multi-operands adder, the 21+1 operands are combined to obtain an updated intermediate result for an iteration step following the previous iteration step, the iteration being continued for such time until all digits of the multiplier have been processed.

Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.

Abstract: An inventive electronic circuit includes central processing means having a clock connection and a data connection, as well as a peripheral unit having a clock connection and a data connection, the clock connection of the peripheral unit being connected to a signal output of a controllable oscillator or to an external clock input. Synchronization means having a first and a second data connection is connected, the first data connection being connected to the data connection of the peripheral unit. In addition a data bus connects the data connection of the CPU and the second data connection of the synchronization means. The clocking of the peripheral unit asynchronous to the central processing unit yields a more effective operation being better adjustable to certain parameters, such as, for example, the application and the energy of the electronic circuit available.

Abstract: An inventive electronic circuit includes a controller for processing a processor task as well as an energy determination means for determining the energy available to the controller. A control means of the electronic circuit controls the controller depending on the energy available to the controller. An optimum utilization of the energy available and, thus, an optimization of the computing speed with maximum energy utilization is achieved by means of the energy control.

Abstract: A method is provided for distinguishing a correct command entry address. To this end, each command word has a prescribed start bit, and long command words have a second start bit for the purpose of distinction.

Abstract: A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomised to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

Abstract: A microprocessor circuit for organizing access to data or programs stored in a memory has a microprocessor, a memory for storing an operating system, and a memory for storing individual external programs. A plurality of memory areas with respective address spaces is provided in the memory for storing the external programs. Each address space is assigned an identifier. The identifier assigned to a memory area is loaded into a first auxiliary register prior to the addressing of the memory area and the identifier of the addressed memory area is loaded into a second auxiliary register. A comparison of the contents of the first and second auxiliary registers is performed. Furthermore, each address space of a memory area is assigned at least one bit sequence defining access rights, whereby code instructions and sensitive data can be protected against write accesses from other external programs.

Abstract: In a method of storing a quantity of data in a target memory location, the data quantity is stored first in a non-volatile buffer memory location. It is then examined whether the data are successfully stored in the non-volatile buffer memory location. If the step of examining produces a positive result, the target memory location to which the predetermined quantity of data is to be written is cleared. After the step of clearing of the target memory location, the data are transferred from the non-volatile buffer memory location to the target memory location. To conclude the storage cycle, the non-volatile buffer memory location is then cleared so as to be available for a new storage operation. The effect achieved thereby is a secure and uncomplicated transfer of information from a source memory to the target memory.

Abstract: A data bus configuration has a data bus which can be operated in a multiplex mode and to which at least one control station and a reception station are connected. The data bus configuration further has a control bus via which the control station can allocate a logical channel to the reception station.