Abstract: A CMOS arrangement is described which has at least one NMOS region (2) and at least one PMOS region (3) and which is provided at its surface with substrate contacts (24, 34), via which it is possible to apply predetermined voltage values to respective substrate sections (1, 30) of the CMOS arrangement. The CMOS arrangement described is distinguished by the fact that the average number of substrate contacts (24, 34) per unit area and/or the average substrate contact area per unit area within the at least one NMOS region (2) is significantly smaller than within the at least one PMOS region (3).

Abstract: The invention relates to a chip card having a card body (2) and a semiconductor chip (3) which is accommodated within the card body (2) and on which a control circuit (7) and a semiconductor memory device, which is electrically coupled to the control circuit (7), are constructed in an integrated manner, which control circuit (7) is supplied with a supply voltage generated by a voltage supply circuit (12) and with a clock generated by a clock supply circuit (13), which is arranged separately from the control circuit (6).

Abstract: A method for automatically determining the high voltage required for programming/erasing an EEPROM wherein the high voltage which is required for erasing or programming each electrically erasable and programmable read-only semiconductor memory is determined individually for each such memory and is stored in the memory itself. This determined high voltage can be called up from the the memory for every further erase or programming operation. Starting from a first value of the high voltage for programming or erasing the memory and a first value of a read voltage for checking the programming or erase operation, the most favorable high voltage is determined by progressively changing either the high voltage or the read voltage.

Abstract: Programmable read-only memory of the EEPROM type, whose memory cells are formed by a memory transistor (ST), which has an insulated gate electrode (FG), and a selection transistor (AT), which is connected in series with the said memory transistor, the drain terminal of a respective selection transistor (AT) being connected to a bit line (BL) and the gate terminal of a respective selection transistor (AT) being connected to a word line (WL), and it being possible to apply a read voltage (U.sub.L ') to the control gate terminal (SG) of the memory transistors (ST), the value of the read voltage (U.sub.L ') depending on the frequency (f.sub.cl) of the reading clock signal (clock1; clock2).

Abstract: A method for driving a field-effect transistor having a source section, a drain section and a gate section, includes applying a gate voltage to the gate section and causing the formation and/or maintenance of an electrically conductive channel between the source section and the drain section. After the channel has been formed, the gate section is disconnected from a gate voltage supply source which applies the gate voltage to the gate section.

Abstract: A circuit configuration having a number of electronic circuit components. The operating state of the circuit components can be set to a reset or erase state by a predetermined control signal applied to the respective circuit component in which state a data content of the circuit component assumes a logic zero value. For the purpose of chronologically successive resetting the data contents of all the circuit components, a selection circuit is provided which is activated to allow the writing of the logic zero value to the circuit components. The selection circuit has a number of opening stages corresponding to the number of circuit components. The opening stages are connected in series one after the other and each circuit component is respectively assigned an opening stage of the selection circuit.

Abstract: A semiconductor component, in particular an EEPROM, and a production method therefor, avoid an avalanche breakdown from a buried channel to a substrate through the use of a special lateral dopant profile in the buried channel, in which a peripheral zone of the buried channel has a higher effective doping than a region located below a tunnel window. The lateral dopant profile is produced through the use of a compensation implantation with dopant atoms of the conduction type opposite that of the buried channel.

Abstract: An EEPROM includes a multiplicity of memory cells which are disposed in a memory cell array and can be addressed through the use of word, bit and source lines for writing, reading out and erasing. The memory cells which can be addressed through a single word line are divided into a multiplicity of groups, of which each is assigned a separate common source line. A method of driving the EEPROM carries out a group-by-group writing to, reading from and/or erasing of the memory cells which can be addressed through a single word line.

Abstract: A cryptographic processer and method for utilizing the "public key code" method of Rivest, Shamir, and Adleman ("RSA method"), for enciphering and deciphering messages wherein two large prime numbers, p and q, and a third large number, E are selected and multiplied to form, N=p*q, converting the message to be encrypted into a series of elements P.sub.i preferably of equal length and having numerical values less than that of N, encrypting these elements P.sub.i by raising each to the power E and subsequently reducing modulus N, to give the numbers C.sub.i =P.sub.i .sup.