Abstract: A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one register, and an auxiliary register that stores a number of bits, each of the bits being assigned to one of the registers of the register bank and indicating whether or not a respective register of the register bank contains information items.

Abstract: A cryptographic processor for performing operations for cryptographic applications comprises a plurality of coprocessors, each coprocessor having a control unit and an arithmetic unit, a central processing unit for controlling said plurality of coprocessors and a bus for connecting each coprocessor to the central processing unit. The central processing unit, the plurality of coprocessors and the bus are integrated an one single chip. The chip further comprises a common power supply terminal for feeding said plurality of coprocessors. By way of parallel connection of various coprocessors, there is obtained an the one hand an increase in throughput and an the other hand an improvement in security of the cryptographic processor with respect to attacks that are based an the evaluation of power profiles of the cryptographic processor, since power profiles of a least two coprocessors are superimposed.

Abstract: In a method for modular multiplying a multiplicand by a multiplier using a modulus, the multiplicand, the multiplier and the modulus being polynomials of variable, a multiplication look-ahead method to obtain a multiplication shift value is carried out. An intermediate result polynomial is shifted to the left by the number of digits of the multiplication shift value to obtain a shifted intermediate result polynomial. Furthermore, a reduction look-ahead method to obtain a reduction shift value is carried out, the reduction shift value equalling the difference of the degree of the shifted intermediate result polynomial and the degree of the modulus polynomial. The modulus polynomial is then shifted by a number of digits equalling the reduction shift value to obtain a shifted modulus polynomial. In a three-operands addition, the shifted intermediate result polynomial and the multiplicand are summed and the shifted modulus polynomial is subtracted to obtain an updated intermediate result polynomial.

Abstract: A pipeline containing a fetch stage, a decode stage, an execute stage, and a write back stage is used for executing a method that provides a higher level of security to a CPU. The write back stage contains at least one register whose use does not result in any state change of the CPU, and at least one register whose use does result in a state change of the CPU. At least one randomly selected code sequence is inserted in the decode stage as a placeholder code or dummy code sequence, making an attack by DPA more difficult.

Abstract: In a method for checking the authenticity of a data medium, in particular a smart card, the encrypted form of a physical feature of the data medium is stored in the data medium. The encrypted form of the feature is transmitted to a terminal, which also measures the physical feature itself. The physical feature is encrypted using a secret key, and is decrypted in the terminal using a public key. Authenticity is confirmed if a comparison of the decrypted feature and the measured feature match. Since the secret key is not contained in either the data medium or the terminal, a high level of security is provided.

Abstract: A data processing method where data to be processed is feed to a processing unit. Supplying a current to the processing unit for operating the processing unit and supplying in a randomly controlled manner a part of the current fed to the processing unit, to an auxiliary circuit.

Abstract: A data carrier, in particular a smart card, is described and has at least one transmitting/receiving antenna and also a rectifier circuit connected downstream thereof and serving for providing a supply voltage for at least one circuit unit. A voltage regulating circuit is connected in parallel with the supply voltage terminals of the circuit unit. The voltage regulating circuit has an output at which a signal proportional to a regulating signal of the voltage regulating circuit can be tapped off. This output is connected to the control input of a controllable clock signal generator, which provides the clock signal for the at least one circuit unit.

Abstract: A device for reliably creating electronic signatures that includes a data carrier read/write device, a data generating device, and a display device. The data carrier read/write device is for receiving a portable data carrier storing a user-specific key and an algorithm used to generate an electronic signature. The data generating device is connected to the data carrier read/write device for transmitting data to the data carrier read/write device. The display device is connected to the data generating device to display the data that has been transmitted to the data carrier read/write device. The data carrier read/write device includes an actuating element operatively connected to the data carrier read/write device and operatively connected to the portable data carrier when the portable data carrier is received by the data carrier read/write device.

Abstract: In a microprocessor configuration, data is temporarily stored in a cache memory or a register bank. A respectively assigned cryptographic unit ensures that the data is encrypted or decrypted when the cache memory or the register bank is accessed. The keyword which is used here is changed if the cache memory or the register no longer contains any valid data to be read out. As a result, an increased protection is obtained against unauthorized monitoring of data and program sequences.

Abstract: A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.

Abstract: In a microcomputer intended for executing a multiplicity of user programs, a memory management unit ensures that none of the user programs can access other programs. However, in order to be able to use common library programs, and at the same time to prevent unchecked access to them, a vector memory area is provided which contains the start addresses of library programs as jump destinations. A library program is called by specifying the vector number, from which the memory management units determines he corresponding address in the vector memory area.

Abstract: A microprocessor configuration includes a data bus for data transfer between functional units. On the bus side, each unit contains an encryption/decryption unit that is controlled synchronously by a random number generator.

Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.

Abstract: A microprocessor for processing various assembler codes, in which a parameter that designates the respective assembler code is provided in the microprocessor and, in dependence on how the parameter is set, a different relative addressing takes place. A method of relative addressing in the microprocessor is also disclosed in which, dependent on an operating state or parameter for the respective assembler code, relative addresses are differently determined.

Abstract: A semiconductor component, in particular an EEPROM, and a production method therefor, avoid an avalanche breakdown from a buried channel to a substrate through the use of a special lateral dopant profile in the buried channel, in which a peripheral zone of the buried channel has a higher effective doping than a region located below a tunnel window. The lateral dopant profile is produced through the use of a compensation implantation with dopant atoms of the conduction type opposite that of the buried channel.

Abstract: An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is provided. A connection supplying the clock signal is connected to the clock input of the respective circuit units via respective controllable switching devices. The control inputs of the switching devices are connected to an output of a random signal generator, so that a circuit unit is operated in parallel or in series with one or more of the other circuit units on the basis of the random signal. A method of operating an integrated semiconductor circuit is also provided.

Abstract: A data carrier, in particular a smart card, is described and has at least one transmitting/receiving antenna and also a rectifier circuit connected downstream thereof and serving for providing a supply voltage for at least one circuit unit. A voltage regulating circuit is connected in parallel with the supply voltage terminals of the circuit unit. The voltage regulating circuit has an output at which a signal proportional to a regulating signal of the voltage regulating circuit can be tapped off. This output is connected to the control input of a controllable clock signal generator, which provides the clock signal for the at least one circuit unit.

Abstract: The invention relates to a semiconductor memory having a non-volatile two-transistor memory cell which has an N-channel selection transistor and an N-channel memory transistor. The drive circuitry for the cell includes a P-channel transfer transistor. A transfer channel is connected to a row line leading to the memory cell. This enables the voltages required for programming to be obtained with relatively little technological complexity.

Abstract: The electronic data-processing device has a processing unit which is connected to one or more memories via a bus. The processing unit has an encryption unit associated with it. One or more secret keys are stored in the one or more memories. All security-related data, and possibly other data as well, are stored in encrypted form in the memory or memories. A comparator compares the stored secret key with a keyword input by a user. The comparator drives a switching unit which in turn drives the encryption unit. Stored data are decrypted only if the comparison is positive.

Abstract: A read-only memory having a multiplicity of memory cells whose contents can be read out with appropriate addressing by word, bit and source lines. The read-only memory is distinguished by the fact that the memory cells which can be addressed via an individual word line are divided into a multiplicity of groups, to each of which a separate common source line is assigned. Accordingly, a group-by-group read-out of the memory cells which can be addressed via an individual word line is carried out.