Patents by Inventor Homayoun Talieh

Homayoun Talieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6867136
    Abstract: The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: March 15, 2005
    Assignee: Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh, Cyprian E. Uzoh
  • Patent number: 6861354
    Abstract: A method for forming conductor structures on a semiconductor wafer is provided. The method begins with depositing a seed layer having a substantially consistent thickness over a barrier layer that covers the features and the field regions among them. The process continues with electrodepositing a planar copper layer on the seed layer and subsequently electroetching it until a thinned seed layer remains over the field regions. When another layer of planar copper is deposited on the remaining copper in the features and on the thinned seed layer on the field regions, this structure minimizes stress related defects in the features which occur during a following anneal process.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: March 1, 2005
    Inventors: Cyprian E. Uzoh, Homayoun Talieh, Bulent M. Basol
  • Publication number: 20050040049
    Abstract: A particular anode assembly can be used to supply a solution for any of a plating operation, a planarization operation, and a plating and planarization operation to be performed on a semiconductor wafer. The anode assembly includes a rotatable shaft disposed within a chamber in which the operation is performed, an anode housing connected to the shaft, and a porous pad support plate attached to the anode housing. The support plate has a top surface adapted to support a pad which is to face the wafer, and, together with the anode housing, defines an anode cavity. A consumable anode may be provided in the anode cavity to provide plating material to the solution. A solution delivery structure by which the solution can be delivered to said anode cavity is also provided. The solution delivery structure may be contained within the chamber in which the operation is performed. A shield can also be mounted between the shaft and an associated spindle to prevent leakage of the solution from the chamber.
    Type: Application
    Filed: August 10, 2004
    Publication date: February 24, 2005
    Inventors: Rimma Volodarsky, Konstantin Volodarsky, Cyprian Uzoh, Homayoun Talieh, Douglas Young
  • Publication number: 20050042873
    Abstract: Systems and methods to operate upon a nonplanar top surface of a conductive surface layer of a workpiece, so as to, for example, preserve the structural integrity of a dielectric film layer disposed below the conductive surface layer, are presented. According to an exemplary method, a layer of conducting material such as a conducting paste is applied over the nonplanar top surface of the conductive surface layer to obtain a planar top surface. At least a portion of the conducting material layer and at least a portion of the conductive surface layer are removed in a planar manner to at least partially planarize the nonplanar top surface. The conducting material layer may be annealed so that the conducting material layer diffuses with the conductive surface layer prior to removal of at least the portions of conducting material layer and the conductive surface layer.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 24, 2005
    Inventors: Cyprian Uzoh, Bulent Basol, Homayoun Talieh
  • Patent number: 6857947
    Abstract: An apparatus for polishing a workpiece includes a workpiece holder configured to hold the workpiece, a polishing member configured to be positioned adjacent to a face of the workpiece in order to polish the workpiece face with a front side of the polishing member, and a platen having a plurality of pressure zones configured to selectively apply pressure to the polishing member thereby causing the polishing member to contact the workpiece face with selective pressure. In another embodiment, the apparatus includes a pressure controller coupled to the platen and configured to selectively adjust the pressure zones.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 22, 2005
    Assignee: ASM NuTool, Inc
    Inventors: Yuchun Wang, Bernard M. Frey, Bulent M. Basol, Homayoun Talieh, Douglas W. Young, Brett E. McGrath, Mukesh Desai, Efrain Velazquez, Tuan Truong
  • Publication number: 20050034976
    Abstract: The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Homayoun Talieh, Cyprian Uzoh
  • Publication number: 20050034994
    Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Jalal Ashjaee, Boguslaw Nagorski, Bulent Basol, Homayoun Talieh, Cyprian Uzoh
  • Patent number: 6855037
    Abstract: The present invention provides a wafer carrier that includes an opening, which in one embodiment is a plurality of holes, disposed along the periphery of the wafer carrier. A gas emitted through the holes onto a peripheral back edge of the wafer assists in preventing the processing liquids and contaminants resulting therefrom from reaching the inner region of the base and the backside inner region of the wafer. In another embodiment, a plurality of concentric sealing members are used to prove a better seal, and the outer seal is preferably independently movable to allow cleaning of a peripheral backside of the wafer to occur while the wafer is still attached to the wafer carrier.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: February 15, 2005
    Assignee: ASM-Nutool, Inc.
    Inventors: Jalal Ashjaee, Homayoun Talieh, Bulent Basol, Konstantin Volodarsky
  • Publication number: 20050029123
    Abstract: The methods and systems described provide for radiation assisted material deposition, removal, and planarization at a surface, edge, and/or bevel of a workpiece such as a semiconductor wafer. Exemplary processes performed on a workpiece surface having topographical features include radiation assisted electrochemical material deposition, which produces an adsorbate layer outside of the features to suppress deposition outside of the features and to encourage, through charge conservation, deposition into the features to achieve, for example, a planar surface profile. A further exemplary process is radiation assisted electrochemical removal of material, which produces an adsorbate layer in the features to suppress removal of material from the features and to encourage, through charge conservation, removal of material outside of the features so that, for example, a planar surface profile is achieved.
    Type: Application
    Filed: August 8, 2003
    Publication date: February 10, 2005
    Inventors: Cyprian Uzoh, Homayoun Talieh, Bulent Basol, Halit Yakupoglu
  • Patent number: 6852630
    Abstract: A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: February 8, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian Uzoh, Halit N. Yakupoglu, Homayoun Talieh
  • Patent number: 6852208
    Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: February 8, 2005
    Assignee: NuTool, Inc.
    Inventors: Jalal Ashjaee, Boguslaw Nagorski, Bulent M. Basol, Homayoun Talieh, Cyprian Uzoh
  • Publication number: 20050016868
    Abstract: Abstract of the Disclosure A system for electrochemical mechanical polishing of a conductive surface of a wafer is provided. The system includes a wafer holder to hold the wafer and a belt pad disposed proximate to the wafer to polish the conductive surface. Application of a potential difference between conductive surface and an electrode and establishing relative motion between the belt pad and the conductive surface result in material removal from the conductive surface. Electrical contact to the surface is provided through either contacts embedded in the belt pad or contacts placed adjacent the belt pad.
    Type: Application
    Filed: April 23, 2004
    Publication date: January 27, 2005
    Applicant: ASM NuTool, Inc.
    Inventors: Bulent Basol, Homayoun Talieh
  • Patent number: 6837979
    Abstract: The present invention provides a method and apparatus for plating a conductive material to a substrate and also modifying the physical properties of a conductive film while the substrate is being plated. The present invention further provides a method and apparatus that plates a conductive material on a workpiece surface in a “proximity” plating manner while a pad type material or other fixed feature is making contact with the workpiece surface in a “cold worked” manner. In this manner, energy stored in the cold worked regions of the plated layer is used to accelerate and enhance micro-structural recovery and growth. Thus, large grain size is obtained in the plated material at a lower annealing temperature and a shorter annealing time.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: January 4, 2005
    Assignee: ASM-Nutool Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh
  • Publication number: 20040259348
    Abstract: In one aspect of the present invention, a method of forming substantially planar conductive structures in cavities on a surface of a workpiece is provided. The method initially forms a large grain layer to overfill the cavities. A small grain conductive layer is formed on the large-grain layer. The small-grain layer has a second material removal rate which is lower than the first material removal rate. During the removal process, the small-grain layer is partially removed so that a small-grain layer portion remains in the recessed portions of the large-grain layer. In the following step, the large-grain layer is continued to be removed at the first material removal rate while the second layer portion is removed at the second material removal rate until the planar conductive structures are formed in the cavities.
    Type: Application
    Filed: April 6, 2004
    Publication date: December 23, 2004
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 6821409
    Abstract: The present invention applies an electrochemical etching solution to a material layer, preferably a metal layer, disposed on a workpiece, in the presence of a current. This electrochemical etching solution supplies to the material on the substrate surface the species to form an intermediate compound on the surface that can be more easily mechanically removed as intermediate compound fragments than the material. By removing the intermediate compound fragments, the process allows more efficient use of the supplied current to form another layer of intermediate compound that can also be mechanically removed, rather than using the current to result in another compound on the surface of the material that eventually dissolves into the solution. In another aspect of the invention, such intermediate compound particulates are externally generated and used to mechanically remove the surface layer of the material.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: November 23, 2004
    Assignee: ASM-Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian E. Uzoh, Paul Lindquist, Homayoun Talieh
  • Patent number: 6815354
    Abstract: A process for forming a conductive structure on a substrate is provided. The substrate has a copper seed layer that is partially exposed through a plurality of openings in a masking layer such as a photoresist. The masking layer is formed on the seed layer. The process electroplates copper through the openings and onto the seed layer. During the copper electroplating process the surface of the masking layer is mechanically swept. The process forms planar conductive material deposits filling the plurality of holes in the masking layer. The upper ends of the conductive deposits are substantially co-planar.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: November 9, 2004
    Assignee: NuTool, Inc.
    Inventors: Cyprian Uzoh, Bulent M. Basol, Homayoun Talieh
  • Publication number: 20040219779
    Abstract: A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.
    Type: Application
    Filed: June 1, 2004
    Publication date: November 4, 2004
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Publication number: 20040195111
    Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.
    Type: Application
    Filed: April 16, 2004
    Publication date: October 7, 2004
    Inventors: Homayoun Talieh, Cyprian Uzoh, Bulent M. Basol
  • Patent number: 6797132
    Abstract: The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: September 28, 2004
    Assignee: Nutool, Inc.
    Inventors: Homayoun Talieh, Cyprian Emeka Uzoh
  • Publication number: 20040168926
    Abstract: The present invention provides a method for forming a conductive film with uniform properties on a wafer surface that has features or cavities. During the process, the workpiece is rotated and laterally moved while an electrodeposition solution is delivered onto the wafer surface at a predetermined flow rate, and a potential difference is applied between the workpiece surface and the electrode. The workpiece is rotated about an axis at predetermined revolutions per minute so that an edge region of the workpiece has a first predetermined linear velocity due to the rotation. The workpiece has a second predetermined linear velocity due to the lateral motion. The second predetermined velocity may be larger than the first predetermined velocity. Further, the wafer may not be rotated.
    Type: Application
    Filed: December 22, 2003
    Publication date: September 2, 2004
    Inventors: Bulent M. Basol, Homayoun Talieh