Patents by Inventor Hon-Lin Huang
Hon-Lin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160049362Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.Type: ApplicationFiled: August 15, 2014Publication date: February 18, 2016Inventors: Yu-Hung Lin, Mei-Hui Fu, Wei-Jung Lin, You-Hua Chou, Chia-Lin Hsu, Hon-Lin Huang, Shih-Chi Lin
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Patent number: 9190347Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.Type: GrantFiled: August 14, 2013Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Jen Lai, You-Hua Chou, Hon-Lin Huang, Huai-Tei Yang
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Publication number: 20140227831Abstract: A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A dielectric buffer layer is formed over at least a portion of the conductive pad, and an under-bump-metallurgy (UBM) is formed directly coupled to the conductive pad, wherein the UBM extends over at least a portion of the dielectric buffer layer. Thereafter, a conductive pillar is formed over the UBM, and one or more conductive materials are formed over the conductive pillar. The substrate may be attached to a carrier substrate using an adhesive.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Patent number: 8759949Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.Type: GrantFiled: February 18, 2010Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hon-Lin Huang, Kuo-Ching Hsu, Chen-Shien Chen
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Patent number: 8736050Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.Type: GrantFiled: July 7, 2010Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20130328215Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jen Lai, You-Hua Chou, Hon-Lin Huang, Huai-Tei Yang
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Patent number: 8541262Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.Type: GrantFiled: September 2, 2010Date of Patent: September 24, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jen Lai, You-Hua Chou, Hon-Lin Huang, Huai-Tei Yang
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Patent number: 8461045Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.Type: GrantFiled: March 17, 2011Date of Patent: June 11, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Hon-Lin Huang
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Patent number: 8158489Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.Type: GrantFiled: March 31, 2010Date of Patent: April 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20120056328Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.Type: ApplicationFiled: September 2, 2010Publication date: March 8, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jen Lai, You-Hua Chou, Hon-Lin Huang, Huai-Tei Yang
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Patent number: 8101499Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.Type: GrantFiled: March 31, 2010Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Patent number: 8097953Abstract: A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.Type: GrantFiled: October 28, 2008Date of Patent: January 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hong Tseng, Kai-Ming Ching, Chen-Shien Chen, Ching-Wen Hsiao, Hon-Lin Huang, Tsung-Ding Wang
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Publication number: 20110165776Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Hon-Lin Huang
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Patent number: 7928534Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.Type: GrantFiled: December 31, 2008Date of Patent: April 19, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Hon-Lin Huang
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Publication number: 20110049706Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.Type: ApplicationFiled: July 7, 2010Publication date: March 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20100330798Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.Type: ApplicationFiled: March 31, 2010Publication date: December 30, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20100276787Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.Type: ApplicationFiled: February 18, 2010Publication date: November 4, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hon-Lin Huang, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20100102453Abstract: A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.Type: ApplicationFiled: October 28, 2008Publication date: April 29, 2010Inventors: Ming-Hong Tseng, Kai-Ming Ching, Chen-Shien Chen, Ching-Wen Hsiao, Hon-Lin Huang, Tsung-Ding Wang
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Publication number: 20100090319Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.Type: ApplicationFiled: December 31, 2008Publication date: April 15, 2010Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Hon-Lin Huang
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Patent number: 7633165Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.Type: GrantFiled: September 8, 2008Date of Patent: December 15, 2009Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Boe Su, Hon-Lin Huang