Patents by Inventor Hong Jung

Hong Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154624
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Application
    Filed: January 15, 2024
    Publication date: May 9, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20240145404
    Abstract: A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.
    Type: Application
    Filed: September 8, 2023
    Publication date: May 2, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Patent number: 11968915
    Abstract: A selector according to an embodiment of the present disclosure includes a first electrode; a second electrode disposed opposite to the first electrode; an ion supply layer disposed between the first electrode and the second electrode to be on the side of the first electrode and doped with a metal, wherein the doped metal diffuses toward the second electrode; a switching layer disposed between the first electrode and the second electrode to be on the side of the second electrode, wherein the doped metal diffuses from the ion supply layer into the switching layer so that metal concentration distribution inside the switching layer is changed to generate metal filaments; and a diffusion control layer inserted between the ion supply layer and the switching layer, wherein the diffusion control layer serves to adjust electrical characteristics related to the generated metal filaments as the amount of the diffusing metal is adjusted in proportion to a thickness of the diffusion control layer.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 23, 2024
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jea Gun Park, Soo Min Jin, Dong Won Kim, Hea Jee Kim, Dae Seong Woo, Sang Hong Park, Sung Mok Jung, Dong Eon Kim
  • Patent number: 11963969
    Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 23, 2024
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho
  • Patent number: 11967462
    Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Sung Kang, Su Yeon Lee, Won Jun Na, Byung Kun Kim, Yu Hong Oh, Sun Hwa Kim, Jae Eun Heo, Hoe Chul Jung
  • Publication number: 20240120300
    Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 11, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240106441
    Abstract: A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 28, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung Min LEE, Gyu Sik KIM, Seung Jin KIM, Jae Hong JUNG
  • Publication number: 20240105695
    Abstract: A display device includes: a pixel circuit layer including a plurality of transistors; first partition wall and a second partition wall on the pixel circuit layer, each of the first and second partition walls having a shape protruding in a thickness direction; a first electrode and a second electrode on the same layer and respectively on the first partition wall and the second partition wall; a light emitting element between the first electrode and the second electrode; and a semiconductor pattern directly on the first electrode.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Tae Gyun KIM, Jun Hong PARK, Jun CHUN, Eui Suk JUNG, Hyun Young JUNG
  • Publication number: 20240103438
    Abstract: A method and a system thereof for producing a digital holographic screen based on multi-hogel printing are proposed. The system includes a light source unit including lasers, a dichroic mirror for RGB three color matching, mirrors, a beam splitter, and an optical shutter, an object beam unit including a spatial filter, a lens, and a mirror, a reference beam unit including a spatial filter, a lens, and a mirror, a diffuser fixing unit including a diffuser holder and a diffuser positioned between the object beam unit and a recording material and configured to scatter and diffuse the object beam, a photomask movement unit including a photomask holder, an XY-translation stage, and a photomask positioned between the reference beam unit and the recording medium and on which a grid-shaped on/off binary pattern is printed, and a controller configured to control the optical shutter and the XY-translation stage.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 28, 2024
    Inventors: Dong Hak SHIN, Yong Seok OH, Jae Hong KIM, Jong sung JUNG, Jae Woo PARK, Jun Yong CHOI
  • Publication number: 20240096758
    Abstract: A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 21, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240091767
    Abstract: A gene amplification chip includes a chamber layer, a cover layer, a bottom layer, an inlet, and an outlet. The chamber layer has a first passage and through holes which are formed on one side of the first passage. The cover layer is disposed on one side of the chamber layer and has a cover channel formed to communicate with the first passage and the through holes, wherein the cover channel, the first passage and the through holes allow passage of liquids in a divided manner. The bottom layer is disposed on another side of the chamber layer and has a bottom channel formed to communicate with the first passage and the through holes. The inlet is formed in the cover layer and communicates with the cover channel. The outlet communicates with any one of the cover channel and the bottom channel.
    Type: Application
    Filed: December 15, 2022
    Publication date: March 21, 2024
    Applicant: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Jae Hong LEE, Won Jong JUNG, Kak NAMKOONG, Hyeong Seok JANG, Jin Ha KIM, Hyung Jun YOUN
  • Publication number: 20240086669
    Abstract: The present invention relates to a frequency selective security paper and a method for manufacturing the same. The frequency selective security paper according to an exemplary embodiment of the present invention may include: a drafting paper for forming a paper; a frequency resonator formed on one surface of the drafting paper and formed in a form of a meandering line or a capacitor so as to resonate to a designated frequency when passing through a security search device; and a coating liquid including the frequency resonator therein and formed on the drafting paper.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 14, 2024
    Applicant: POSI INC.
    Inventors: Yu Suk JUNG, Jae Hong JUNG
  • Publication number: 20240088057
    Abstract: A chip package with at least one electromagnetic interference (EMI) shielding layer and at least one ground wire and a method of manufacturing the same are provided. The chip package includes a chip package unit, at least one EMI shielding layer, and at least one ground wire. The ground wire which consists of a first end and a second end opposite to the first end is inserted through the EMI shielding layer and a first insulating layer of the chip package unit. The first end is electrically connected with the EMI shielding layer while the second end of the ground wire is electrically connected with at least one grounding end of at least one first circuit layer of the chip package unit for protection against static electricity. Thereby malfunction of an electronic system with semiconductor chips due to static electricity can be avoided.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 14, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240088168
    Abstract: A display device includes: a first substrate; a second substrate on the first substrate and exposing a first edge portion of the first substrate, the second substrate protruding beyond a second edge portion of the first substrate; a connection line on the first edge portion of the first substrate, the connection line having a first end portion protruding beyond a first side of the second substrate and a second end portion covered by the second substrate; and a thin-film transistor layer on the second substrate and connected to the connection line. The thin-film transistor layer includes signal lines extending from the first side to a second side of the second substrate. The signal lines extend into contact openings in the thin-film transistor layer and are exposed at a lower part of the second substrate on the second side of the second substrate.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Tae Gyun KIM, Jun Hong PARK, Eui Suk JUNG
  • Publication number: 20240088370
    Abstract: The present invention relates to an apparatus and a method for manufacturing a lithium electrode, comprising a cutting stage, a laser irradiation portion and a lithium metal film supply portion, in which a plurality of adsorption holes and a plurality of unit electrode pattern grooves are formed on the upper surface of the cutting stage.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Gi Su PARK, Minsun SONG, Jaegil LEE, Kyungsik HONG, Jong Mo JUNG
  • Publication number: 20240078990
    Abstract: The present invention relates to a polyester sound absorption material having improved moldability and decreased weight and a method of manufacturing a molded product using the same, and more particularly to a polyester sound absorption material, which is capable of integrally molding a skin member and a sound absorption material using a felt including a polyester base fiber, a low-melting-point polyester adhesive fiber and a polyester hollow fiber, without the need to attach an additional sound absorption pad onto a skin member.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 7, 2024
    Inventors: Hong Mo Koo, Mi Jung Yun, Joon Yong Song, Hyun Dae Cho, Hyung Joon Youn, Jeong Wook Lee
  • Publication number: 20240078688
    Abstract: Disclosed is a device, for matching oral scan data, comprising a first matching unit, a teeth segmentation unit, and a second matching unit. The first matching unit matches a coordinate system of three-dimensional oral scan data to a coordinate system of a three-dimensional oral computed tomography (CT) image by using three-dimensional feature points of the three-dimensional oral scan data and three-dimensional feature points of the three-dimensional oral CT image. The teeth segmentation unit segments teeth from the three-dimensional oral scan data on the basis of the three-dimensional feature points of the three-dimensional oral scan data to generate surface information relating to the segmented teeth. The second matching unit matches the three-dimensional oral scan data and the three-dimensional oral CT image, which have matching coordinate systems, by means of the surface information.
    Type: Application
    Filed: January 20, 2022
    Publication date: March 7, 2024
    Applicant: HDX WILL CORP.
    Inventors: Hong Jung, Sung Min Lee, Bo Hyun Song
  • Publication number: 20240070882
    Abstract: Disclosed is a three-dimensional oral scan data matching device including a matching unit, a deep-learning unit, a scanned frame feature determination unit, and a scan data re-matching unit. The matching unit matches a plurality of scanned frames to generate a full mouth image. The deep-learning unit performs deep-learning to detect a feature of the full mouth image. The scanned frame feature determination unit determines a feature of the plurality of scanned frames by utilizing the feature of the full mouth image. The scan data re-matching unit re-matches the plurality of scanned frames on the basis of the feature of the plurality of scanned frames, to reconstruct a three-dimensional oral model.
    Type: Application
    Filed: January 13, 2022
    Publication date: February 29, 2024
    Applicant: HDX WILL CORP.
    Inventors: Hong Jung, Sung Min Lee, Bo Hyun Song
  • Publication number: 20240065816
    Abstract: Disclosed is a device for matching three-dimensional intra-oral scan data, the device comprising a computed tomography (CT) image depth map generation unit, a depth map coordinate difference information determination unit, a depth map correction unit, and an intra-oral scan model recovery unit. The CT image depth map generation unit generates a depth map of a CT frame from a CT image by using information about a single scan frame of the scan data. The depth map coordinate difference information determination unit determines depth map coordinate difference information between the depth map of the CT frame and a depth map of the scan frame. The depth map correction unit corrects the depth map of the scan frame on the basis of the depth map coordinate difference information. The intra-oral scan model recovery unit recovers a three-dimensional intra-oral scan model on the basis of the corrected depth map of the scan frame.
    Type: Application
    Filed: January 17, 2022
    Publication date: February 29, 2024
    Applicant: HDX WILL CORP.
    Inventors: Hong Jung, Sung Min Lee, Bo Hyun Song
  • Patent number: D1024051
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng