Abstract: Disclosed is a device for matching three-dimensional intra-oral scan data, the device comprising a computed tomography (CT) image depth map generation unit, a depth map coordinate difference information determination unit, a depth map correction unit, and an intra-oral scan model recovery unit. The CT image depth map generation unit generates a depth map of a CT frame from a CT image by using information about a single scan frame of the scan data. The depth map coordinate difference information determination unit determines depth map coordinate difference information between the depth map of the CT frame and a depth map of the scan frame. The depth map correction unit corrects the depth map of the scan frame on the basis of the depth map coordinate difference information. The intra-oral scan model recovery unit recovers a three-dimensional intra-oral scan model on the basis of the corrected depth map of the scan frame.

Abstract: Disclosed is a three-dimensional oral scan data matching device including a matching unit, a deep-learning unit, a scanned frame feature determination unit, and a scan data re-matching unit. The matching unit matches a plurality of scanned frames to generate a full mouth image. The deep-learning unit performs deep-learning to detect a feature of the full mouth image. The scanned frame feature determination unit determines a feature of the plurality of scanned frames by utilizing the feature of the full mouth image. The scan data re-matching unit re-matches the plurality of scanned frames on the basis of the feature of the plurality of scanned frames, to reconstruct a three-dimensional oral model.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: An embodiment mobility for delivering articles includes a frame defining a body of the mobility, a chain member coupled to a first side of the frame, wherein the chain member has a closed curve shape along an up-down direction, is movable relative to the frame, and includes a standby section provided at a fixed position with respect to the frame irrespective of a movement of the chain member, wherein the standby section includes a plurality of bent areas, a tray member having a first side coupled to the chain member, the tray member being movable in connection with a movement of the chain member, a wheel coupled to a lower portion of the frame, and a driver configured to provide a driving force to the chain member.

Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

Abstract: Disclosed is a hydrogen recirculation ejector for fuel cells including a recirculation line configured to recirculate residual hydrogen gas discharged from a fuel cell stack configured to generate electricity using air and hydrogen gas supplied thereto to an inlet of the fuel cell stack and an ejector including a nozzle installed on the recirculation line, the nozzle being configured to supply new hydrogen gas, a venturi tube configured to mix the hydrogen supplied from the nozzle and the recirculated hydrogen with each other, and a diffuser configured to supply the mixed hydrogen gas to the fuel cell stack, wherein the nozzle includes a hydrogen introduction portion, a ring-shaped inner wall, a ring-shaped outer wall, a ring-shaped front end wall, and a ring-shaped rear end wall, and wherein the thickness of the inner wall and/or the outer wall is gradually increased with increasing distance from the hydrogen introduction portion.

Abstract: Provided herein are methods of using human placental stem cells in the treatment of subjects having acute kidney injury (AKI).

Abstract: An embodiment mobility for delivering articles includes a frame defining a body of the mobility, a chain member coupled to a first side of the frame, wherein the chain member has a closed curve shape along an up-down direction, is movable relative to the frame, and includes a standby section provided at a fixed position with respect to the frame irrespective of a movement of the chain member, wherein the standby section includes a plurality of bent areas, a tray member having a first side coupled to the chain member, the tray member being movable in connection with a movement of the chain member, a wheel coupled to a lower portion of the frame, and a driver configured to provide a driving force to the chain member.

Abstract: The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.

Abstract: A display device includes a substrate having a display area and a non-display area; a first transistor that is disposed on the substrate and that overlaps the display area; a first pixel defining layer disposed on the first transistor; a first emission layer disposed in the first pixel defining layer; a second pixel defining layer that is disposed on the substrate and that overlaps the non-display area; a second emission layer disposed in the second pixel defining layer; a second electrode disposed on the first emission layer and the second emission layer; and an encapsulation organic layer disposed on the second electrode, wherein the encapsulation organic layer overlaps the first pixel defining layer and the second pixel defining layer, and an end of the encapsulation organic layer is disposed inside the second pixel defining layer.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.

Abstract: The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.