Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

Abstract: The present invention provides methods for increasing expression of ICOS on an effector T cell comprising contacting said effector T cell with an anti-PD-1 antibody. The present invention also provides methods for decreasing expression of ICOS on a regulatory T cell comprising contacting said regulatory T cell with an anti-PD-1 antibody. The present invention provides methods for increasing sensitivity to an agent directed to ICOS in a human comprising administering to the human an anti-PD1 antibody. The present invention also provides methods of treating cancer in a human in need thereof comprising administering an anti-PD-1 antibody and an anti-ICOS antibody to said human, wherein the anti-PD-1 antibody increases T cell sensitivity to the ICOS antibody.

Abstract: An integrated circuit device having a vertical connection interfaces for coupling stacked components are provided that improve communication between the stacked components. The techniques described herein allow for increased signal connection density while reducing potential for crosstalk. For example, a ground to signal ratio of connections between components in a vertical interface configured to carry ground signals relative to connections configured to carry data signals within a bank of connections has an edge to center gradient which reduces the amount of ground connections needed to meet crosstalk thresholds, while increasing the amount of signal connections available for communication between components across the vertical interface.

Abstract: According to one aspect of the present invention, there is provided a method for performing storage control. Member storage media and a hot spare storage medium are identified in a storage system. The member storage media are members of a storage medium array, and the hot spare storage medium is for joining in the storage medium array when a member storage medium fails. Data on a member storage medium having a write amplification effect is migrated to the hot spare storage medium. In the member storage medium having a write amplification effect, an erase operation is performed on a storage medium where the migrated data is located. Embodiments of the present invention can alleviate adverse impact caused by a write amplification effect.

Abstract: An integrated circuit device having a vertical connection interfaces for coupling stacked components are provided that improve communication between the stacked components. The techniques described herein allow for increased signal connection density while reducing potential for crosstalk. For example, a ground to signal ratio of connections between components in a vertical interface configured to carry ground signals relative to connections configured to carry data signals within a bank of connections has an edge to center gradient which reduces the amount of ground connections needed to meet crosstalk thresholds, while increasing the amount of signal connections available for communication between components across the vertical interface.

Abstract: An interface layout for a vertical interface of a first semiconductor component is disclosed. A first one or more conductors configured to carry power signals extends vertically from the first semiconductor component. A second one or more conductors configured to carry data signals extends vertically from the first semiconductor component. A third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component. The first one or more conductors are further configured to shield and separate the second one or more conductors. A fourth one or more conductors extends horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors. A fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors.

Abstract: According to one aspect of the present invention, there is provided a method for performing storage control. Member storage media and a hot spare storage medium are identified in a storage system. The member storage media are members of a storage medium array, and the hot spare storage medium is for joining in the storage medium array when a member storage medium fails. Data on a member storage medium having a write amplification effect is migrated to the hot spare storage medium. In the member storage medium having a write amplification effect, an erase operation is performed on a storage medium where the migrated data is located. Embodiments of the present invention can alleviate adverse impact caused by a write amplification effect.

Abstract: According to one aspect of the present invention, there is provided a method for performing storage control. Member storage media and a hot spare storage medium are identified in a storage system. The member storage media are members of a storage medium array, and the hot spare storage medium is for joining in the storage medium array when a member storage medium fails. Data on a member storage medium having a write amplification effect is migrated to the hot spare storage medium. In the member storage medium having a write amplification effect, an erase operation is performed on a storage medium where the migrated data is located. Embodiments of the present invention can alleviate adverse impact caused by a write amplification effect.

Abstract: An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.

Abstract: A grasping apparatus for grasping an object includes at least two grasping portions and at least two pressure sensing mechanisms disposed in the corresponding grasping portions. The pressure sensing mechanism detects a grasping force between the grasping portions while grasping the object. The pressure sensing mechanism includes two parallel metal films and an elastic portion therebetween. The elastic portion deforms to decrease the distance between the metal films for sensing the grasping force.

Abstract: Embodiments of the present disclosure provide a method and apparatus for storage control. The method comprises: in response to having received a data deletion command on sensitive data, marking a storage medium page where the sensitive data is located as invalid, and putting a storage medium block where the storage medium page is located in a garbage collection queue, wherein the storage medium block is a minimum unit of storage medium erasure in a SSD; determining a secure deletion time corresponding to the sensitive data; in response to a remaining time to a next garbage collection being longer than the secure deletion time corresponding to the sensitive data, setting a value of the remaining time as the secure deletion time; and triggering a garbage collection according to the remaining time. Using the solution according to the embodiment of the present disclosure, the security of the SSD can be enhanced.

Abstract: A grasping apparatus for grasping an object includes at least two grasping portions and at least two pressure sensing mechanisms disposed in the corresponding grasping portions. The pressure sensing mechanism detects a grasping force between the grasping portions while grasping the object. The pressure sensing mechanism includes two parallel metal films and an elastic portion therebetween. The elastic portion deforms to decrease the distance between the metal films for sensing the grasping force.

Abstract: An integrated circuit package substrate may include a core layer and dielectric layers formed on top and bottom surfaces of the core layer. Routing traces such as stripline structures may be formed in some of the dielectric layers, whereas plated through hole (PTH) structures may be formed through the core layer. A first pair of PTHs that carry a first differential signal may be orthogonally intertwined with a second pair of PTHs that carry a second differential signal. Solder balls formed at the surface of the package substrate may include a first pair of solder balls that convey a first differential signal that is orthogonally intertwined with respect to a second pair of solder balls that convey a second differential signal. The package substrate may be mounted on a printed circuit board (PCB). Differential PCB vias could use the same BGA orthogonal pattern described above.

Abstract: An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.

Abstract: An improved power distribution network comprises a substrate, an integrated circuit mounted on the substrate, first and second tunable decoupling capacitors mounted on the substrate, and a third decoupling capacitor formed in the integrated circuit. The power supply pin is connected to the first, second, and third capacitors; and the first and second capacitors are connected to the third capacitor as well. The capacitance values of the first and second tunable decoupling capacitors may be adjusted to reduce the magnitude of the system level impedance at least at those frequencies having substantial signal jitter to power noise sensitivity.

Abstract: An integrated circuit package having a package substrate, an integrated circuit, and at least one solder ball is provided. The package substrate has first and second surfaces. The integrated circuit may be mounted on the first surface of the package substrate. The solder ball may be coupled to the second surface of the package substrate. The package substrate may include a substrate layer. The substrate layer may include a ground plane with an opening. The opening may be formed just above the solder ball. In one instance, the diameter of the opening is greater than the diameter of the solder ball pad.

Abstract: According to one aspect of the present invention, there is provided a method for performing storage control. Member storage media and a hot spare storage medium are identified in a storage system. The member storage media are members of a storage medium array, and the hot spare storage medium is for joining in the storage medium array when a member storage medium fails. Data on a member storage medium having a write amplification effect is migrated to the hot spare storage medium. In the member storage medium having a write amplification effect, an erase operation is performed on a storage medium where the migrated data is located. Embodiments of the present invention can alleviate adverse impact caused by a write amplification effect.

Abstract: Embodiments of the invention generally provide an electronic device comprising an electrical interconnect component that includes an electrical trace. The electrical trace has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace have a thickness that is less than the skin depth, the current flows through substantially the entire cross-sectional area of the electrical trace for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.