Patents by Inventor Hong-Bae Park
Hong-Bae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973209Abstract: A positive electrode active material for a secondary battery includes a lithium composite transition metal oxide including nickel (Ni), cobalt (Co), and manganese (Mn), wherein the lithium composite transition metal oxide has a layered crystal structure of space group R3m, includes the nickel (Ni) in an amount of 60 mol % or less based on a total amount of transition metals, includes the cobalt (Co) in an amount greater than an amount of the manganese (Mn), and is composed of single particles.Type: GrantFiled: June 7, 2019Date of Patent: April 30, 2024Assignee: LG Chem, Ltd.Inventors: Eun Hee Lee, Seong Bae Kim, Young Su Park, Yi Rang Lim, Hong Kyu Park, Song Yi Yang, Byung Hyun Hwang, Woo Hyun Kim
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Patent number: 11973222Abstract: A positive electrode active material precursor having a uniform particle size distribution and represented by Formula 1, wherein a percentage of fine powder with an average particle diameter (D50) of 1 ?m or less is generated when the positive electrode active material precursor is rolled at 2.5 kgf/cm2 is less than 1%, and an aspect ratio is 0.93 or more, and a method of preparing the positive electrode active material precursor [NixCoyM1zM2w](OH)2 ??[Formula 1] in Formula 1, 0.5?x<1, 0<y?0.5, 0<z?0.5, and 0?w?0.1, M1 includes at least one selected from the group consisting of Mn and Al, and M2 includes at least one selected from the group consisting of Zr, B, W, Mo, Cr, Nb, Mg, Hf, Ta, La, Ti, Sr, Ba, Ce, F, P, S, and Y. A method of preparing the positive electrode active material precursor is also provided.Type: GrantFiled: December 7, 2018Date of Patent: April 30, 2024Assignee: LG Chem, Ltd.Inventors: Seong Bae Kim, Yi Rang Lim, Kyoung Wan Park, Hyun Uk Kim, Hong Kyu Park, Chang Jun Moon, Eun Hee Kim
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Patent number: 11705503Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.Type: GrantFiled: September 30, 2020Date of Patent: July 18, 2023Inventors: Jin Bum Kim, MunHyeon Kim, Hyoung Sub Kim, Tae Jin Park, Kwan Heum Lee, Chang Woo Noh, Maria Toledano Lu Que, Hong Bae Park, Si Hyung Lee, Sung Man Whang
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Publication number: 20230187446Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: ApplicationFiled: December 16, 2022Publication date: June 15, 2023Inventors: Min-Seok JO, Jae-Hyun LEE, Jong-Han LEE, Hong-Bae PARK, Dong-Soo LEE
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Patent number: 11532624Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: GrantFiled: December 12, 2018Date of Patent: December 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Seok Jo, Jae-Hyun Lee, Jong-Han Lee, Hong-Bae Park, Dong-Soo Lee
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Publication number: 20220223702Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Chang-yeon LEE, Jin-wook LEE, Min-chan GWAK, Kye-Hyun BAEK, Hong-bae PARK
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Patent number: 11309393Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.Type: GrantFiled: May 7, 2019Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-yeon Lee, Jin-wook Lee, Min-chan Gwak, Kye-Hyun Baek, Hong-bae Park
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Publication number: 20210013324Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Jin Bum KIM, MunHyeon KIM, Hyoung Sub KIM, Tae Jin PARK, Kwan Heum LEE, Chang Woo NOH, Maria TOLEDANO LU QUE, Hong Bae PARK, Si Hyung LEE, Sung Man WHANG
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Patent number: 10651179Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: May 30, 2018Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
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Patent number: 10636886Abstract: A semiconductor device includes a first fin type pattern and a second fin type pattern, which are isolated from each other by an isolating trench, and extend in a first direction on a substrate, respectively, a third fin type pattern which is spaced apart from the first fin type pattern and the second fin type pattern in a second direction and extends in the first direction, a field insulation film on a part of sidewalls of the first to third fin type patterns, a device isolation structure, which extends in the second direction, and is in the isolating trench, a gate insulation support, which extends in the first direction on the field insulation film between the first fin type pattern and the third fin type pattern, a gate structure, which intersects the third fin type pattern, extends in the second direction, and is in contact with the gate insulation support, wherein a height from the substrate to a bottom surface of the gate structure is greater than a height from the substrate to a bottom surface of theType: GrantFiled: November 1, 2018Date of Patent: April 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min Seok Jo, Jae Hyun Lee, Jong Han Lee, Hong Bae Park
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Publication number: 20200035796Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.Type: ApplicationFiled: May 7, 2019Publication date: January 30, 2020Inventors: Chang-yeon LEE, Jin-wook LEE, Min-chan GWAK, Kye-Hyun BAEK, Hong-bae PARK
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Publication number: 20190363084Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: ApplicationFiled: December 12, 2018Publication date: November 28, 2019Inventors: Min-Seok JO, Jae-Hyun LEE, Jong-Han LEE, Hong-Bae PARK, Dong-Soo LEE
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Publication number: 20190305099Abstract: A semiconductor device includes a first fin type pattern and a second fin type pattern, which are isolated from each other by an isolating trench, and extend in a first direction on a substrate, respectively, a third fin type pattern which is spaced apart from the first fin type pattern and the second fin type pattern in a second direction and extends in the first direction, a field insulation film on a part of sidewalls of the first to third fin type patterns, a device isolation structure, which extends in the second direction, and is in the isolating trench, a gate insulation support, which extends in the first direction on the field insulation film between the first fin type pattern and the third fin type pattern, a gate structure, which intersects the third fin type pattern, extends in the second direction, and is in contact with the gate insulation support, wherein a height from the substrate to a bottom surface of the gate structure is greater than a height from the substrate to a bottom surface of theType: ApplicationFiled: November 1, 2018Publication date: October 3, 2019Inventors: Min Seok JO, Jae Hyun LEE, Jong Han LEE, Hong Bae PARK
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Publication number: 20190198639Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.Type: ApplicationFiled: July 17, 2018Publication date: June 27, 2019Inventors: Jin Bum KIM, MunHyeon KIM, Hyoung Sub KIM, Tae Jin PARK, Kwan Heum LEE, Chang Woo NOH, Maria TOLEDANO LU QUE, Hong Bae PARK, Si Hyung LEE, Sung Man WHANG
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Publication number: 20180277547Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: May 30, 2018Publication date: September 27, 2018Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
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Patent number: 10014304Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: October 25, 2016Date of Patent: July 3, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
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Publication number: 20170040328Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: October 25, 2016Publication date: February 9, 2017Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
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Patent number: 9543300Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: GrantFiled: February 26, 2016Date of Patent: January 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong
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Patent number: 9508727Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: September 14, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
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Publication number: 20160204108Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: ApplicationFiled: February 26, 2016Publication date: July 14, 2016Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong