Patents by Inventor Hongyong Zhang

Hongyong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5882960
    Abstract: A semiconductor device is disclosed. The semiconductor device has a crystalline silicon film as an active layer region. The crystalline silicon film has needle-like or columnar crystals oriented parallel to the substrate and having a crystal growth direction of (111) axis. A method for preparing the semiconductor device comprises steps of adding a catalytic element to an amorphous silicon film; and heating the amorphous silicon film containing the catalytic element at a low temperature to crystallize the silicon film.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: March 16, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani, Junichi Takeyama
  • Patent number: 5879969
    Abstract: In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: March 9, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura
  • Patent number: 5879977
    Abstract: A process for fabricating a semiconductor by crystallizing a silicon film in a substantially amorphous state by annealing it at a temperature not higher than the crystallization temperature of amorphous silicon, and it comprises forming selectively, on the surface or under an amorphous silicon film, a coating, particles, clusters, and the like containing nickel, iron, cobalt, platinum or palladium either as a pure metal or a compound thereof such as a silicide, a salt, and the like, shaped into island-like portions, linear portions, stripes, or dots; and then annealing the resulting structure at a temperature lower than the crystallization temperature of an amorphous silicon by 20.degree. to 150.degree. C.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: March 9, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideki Uochi, Toru Takayama, Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 5861337
    Abstract: A method for manufacturing a semiconductor device including preparing a multi-chamber system having at least first and second chambers, the first chamber for forming a film and the second chamber for processing an object with a laser light; processing a substrate in one of the first and second chambers; transferring the substrate to the other one of the first and second chambers; and processing the substrate in the other one of the chambers, wherein the first and second chambers can be isolated from one another by using a gate valve.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: January 19, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 5858473
    Abstract: A laser annealing process for recovering crystallinity of a deposited semiconductor film such as of silicon which had undergone morphological damage, said process comprising activating the semiconductor by irradiating a pulsed laser beam operating at a wavelength of 400 nm or less and at a pulse width of 50 nsec or less onto the surface of the film, wherein,said deposited film is coated with a transparent film such as a silicon oxide film at a thickness of from 3 to 300 nm, and the laser beam incident to said coating is applied at an energy density E (mJ/cm.sup.2) provided that it satisfies the relation:log.sub.10 N.ltoreq.-0.02(E-350),where N is the number of shots of the pulsed laser beam.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: January 12, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Hiroaki Ishihara
  • Patent number: 5849043
    Abstract: A process for laser processing an article, which comprises: heating the intended article to be doped with an impurity to a temperature not higher than the melting point thereof, said article being made from a material selected from a semiconductor, a metal, an insulator, and a combination thereof; and irradiating a laser beam to the article in a reactive gas atmosphere containing said impurity, thereby allowing the impurity to physically or chemically diffuse into, combine with, or intrude into said article.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: December 15, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 5849611
    Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: December 15, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi
  • Patent number: 5843225
    Abstract: A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400.degree. to 650.degree. C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 1, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Yasuhiko Takemura, Hongyong Zhang, Shunpei Yamazaki
  • Patent number: 5837619
    Abstract: Method of fabricating a semiconductor device. A glass substrate such as Corning 7059 is used as a substrate. A bottom film is formed. Then, the substrate is annealed above the strain point of the glass substrate. The substrate is then slowly cooled below the strain point. Thereafter, a silicon film is formed, and a TFT is formed. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps. This makes it easy to perform mask alignments. Furthermore, defects due to misalignment of masks are reduced, and the production yield is enhanced. In another method, a glass substrate made of Corning 7059 is also used as a substrate. The substrate is annealed above the strain point. Then, the substrate is rapidly cooled below the strain point. Thereafter, a bottom film is formed, and a TFT is fabricated. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: November 17, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Adachi, Yuugo Goto, Hongyong Zhang, Toru Takayama
  • Patent number: 5830786
    Abstract: A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: November 3, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideki Uochi, Shunpei Yamazaki, Yasuhiko Takemura, Minoru Miyazaki, Akane Murakami, Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
  • Patent number: 5830784
    Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where lead serving as a crystallization-promoting catalyst is introduced.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: November 3, 1998
    Assignee: Semiconductor Energy Laboratory Company, Ltd.
    Inventors: Hongyong Zhang, Toru Takayama
  • Patent number: 5824573
    Abstract: Nickel is introduced to a peripheral circuit section and a picture element section on an amorphous silicon film to crystallize them. After forming gate electrodes and others, a source, drain and channel are formed by doping impurities, and laser is irradiated to improve the crystallization. After that, electrodes/wires are formed. Thereby an active matrix type liquid crystal display whose thin film transistors (TFT) in the peripheral circuit section are composed of the crystalline silicon film crystal-grown in the direction parallel to the flow of carriers and whose TFTs in the picture element section are composed of the crystalline silicon film crystal-grown in the direction vertical to the flow of carriers can be obtained.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 20, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura
  • Patent number: 5818076
    Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic ?110! axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: October 6, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani
  • Patent number: 5814529
    Abstract: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: September 29, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 5811328
    Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: September 22, 1998
    Assignee: Semiconductor Energy Laboratory Co, Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 5795795
    Abstract: A method of fabricating a semiconductor device by the use of laser crystallization steps is provided. During these crystallization steps, an amorphous or polycrystalline semiconductor is crystallized by laser irradiation in such a way that generation of ridges is suppressed. Two separate laser crystallization steps are carried out. First, a laser irradiation step is performed in a vacuum, using somewhat weak laser light. Then, another laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient with intenser laser light. The first laser irradiation conducted in a vacuum does not result in satisfactory crystallization. However, this irradiation can suppress generation of ridges. The second laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient to achieve sufficient crystallization, but no ridges are produced.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: August 18, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takamasa Kousai, Hongyong Zhang, Akiharu Miyanaga
  • Patent number: 5783468
    Abstract: Method of fabricating a semiconductor circuit is initiated with formation of an amorphous silicon film. Then, a second layer containing at least one catalytic element is so formed as to be in intimate contact with the amorphous silicon film, or the catalytic element is introduced into the amorphous silicon film. This amorphous silicon film is selectively irradiated with laser light or other equivalent intense light to crystallize the amorphous silicon film.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: July 21, 1998
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura
  • Patent number: 5777701
    Abstract: A metal electrode also serving as a black matrix is so formed as to cover the periphery of an ITO pixel electrode. A region where the pixel electrode and the metal electrode coextend also serves as an auxiliary capacitor. Since the auxiliary capacitor can be formed by using a thin insulating film, it can have a large capacitance. By virtue of the structure in which the black matrix also serves as the auxiliary capacitor, it is not necessary to provide an electrode dedicated to the auxiliary capacitor, thereby preventing reduction in aperture ratio. Further, the black matrix can completely shield a source line and a gate line from light.
    Type: Grant
    Filed: May 7, 1996
    Date of Patent: July 7, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 5773846
    Abstract: A thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: June 30, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura
  • Patent number: 5773327
    Abstract: A method for improving the reliability and yield of a thin film transistor by controlling the crystallinity thereof. The method comprises the steps of forming a gate electrode on an island amorphous silicon film, injecting an impurity using the gate electrode as a mask, forming a coating film containing at least one of nickel, iron, cobalt, platinum and palladium so that it adheres to parts of the impurity regions, and annealing it at a temperature lower than the crystallization temperature of pure amorphous silicon to advance the crystallization starting therefrom and to crystallize the impurity regions and channel forming region.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: June 30, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura