Patents by Inventor Hongyu Liu

Hongyu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100110760
    Abstract: Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
    Type: Application
    Filed: February 23, 2009
    Publication date: May 6, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Henry Huang, Hongyue Liu
  • Publication number: 20100110756
    Abstract: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Maroun Georges Khoury, Hongyue Liu, Brian Lee, Andrew John Gjevre Carter
  • Publication number: 20100109656
    Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.
    Type: Application
    Filed: February 9, 2009
    Publication date: May 6, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
  • Publication number: 20100097841
    Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
    Type: Application
    Filed: June 18, 2009
    Publication date: April 22, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
  • Publication number: 20100097852
    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Publication number: 20100100857
    Abstract: Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Applicant: Seagate Technology LLC
    Inventors: Yiran Chen, Dadi Setiadi, Hai Li, Haiwen Xi, Hongyue Liu
  • Publication number: 20100096611
    Abstract: A device including a transistor that includes a source region; a drain region; and a channel region, wherein the channel region electrically connects the source region and the drain region along a channel axis; and a memory cell, wherein the memory cell is disposed adjacent the drain region so that the channel axis runs through the memory cell.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu
  • Publication number: 20100095050
    Abstract: Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Hongyue Liu, Hai Li
  • Publication number: 20100095052
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.
    Type: Application
    Filed: June 11, 2009
    Publication date: April 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Yuan Yan, Harry Hongyue Liu
  • Publication number: 20100091546
    Abstract: One time programmable memory units include a magnetic tunnel junction cell electrically coupled to a bit line and a word line. The magnetic tunnel junction cell is pre-programmed to a first resistance state, and is configured to switch only from the first resistance state to a second resistance state by passing a voltage across the magnetic tunnel junction cell. In some embodiments, a transistor is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. In other embodiments, a device having a rectifying switching characteristic, such as a diode or other non-ohmic device, is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. Methods of pre-programming the one time programmable memory units and reading and writing to the units are also disclosed.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hongyue Liu, Xuguang Wang, Yong Lu, Yiran Chen
  • Publication number: 20100091550
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage with dummy resistive sense element regions. A first resistance distribution is obtained for a first dummy region of resistance sense elements and a second resistance distribution is obtained for a second dummy region of resistive sense elements. A user resistive sense element from a user region is assigned to a selected resistive sense element of one of the first or second dummy regions in relation to the first and second resistance distributions.
    Type: Application
    Filed: July 13, 2009
    Publication date: April 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Yuan Yan, Harry Hongyue Liu
  • Publication number: 20100095057
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Henry F. Huang
  • Publication number: 20100091562
    Abstract: A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.
    Type: Application
    Filed: October 13, 2008
    Publication date: April 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Henry F. Huang, Yong Lu
  • Publication number: 20100080053
    Abstract: The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Xuguang Wang
  • Publication number: 20100073984
    Abstract: A register having a track with a first electrode is at the first end to supply a current to the track in a first direction and a second electrode at the second end to supply a current to the track in a second direction, the second direction being opposite to the first direction. A first domain wall anchor and a second domain wall anchor are positioned proximate the track between the first electrode and the second electrode. Each of the domain wall anchors has a ferromagnetic pinned layer and a barrier layer proximate the track, with the barrier layer between the track and the ferromagnetic pinned layer. The ferromagnetic layer has a magnetization orientation pinned perpendicular to the magnetization orientation of the track.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 25, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Dimitar V. Dimitrov, Andreas Roelofs, Xiaobin Wang, Paul E. Anderson, Hongyue Liu
  • Publication number: 20100067282
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 18, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • Publication number: 20100067281
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 18, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Publication number: 20100057984
    Abstract: A storage system that includes non-volatile main memory; non-volatile read cache; non-volatile write cache; and a data path operably coupled between the non-volatile write cache and the non-volatile read cache, wherein the storage system does not include any volatile cache and methods for retrieving and writing data throughout this memory hierarchy system.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Haiwen Xi, Song S. Xue
  • Publication number: 20100058125
    Abstract: A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Publication number: 20100054026
    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue