Patents by Inventor Howard E. Rhodes

Howard E. Rhodes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer dicing using scribe line etch
    Patent number: 8071429
    Abstract: Embodiments of a method for separating dies from a wafer having first and second sides. The process embodiment includes masking the first side of the wafer, the mask including openings therein to expose parts of the first side substantially aligned with scribe lines of the wafer. The process embodiment also includes etching from the exposed parts of the first side of the wafer until an intermediate position between the first and second sides and sawing the remainder of the wafer, starting from the intermediate position until reaching the second surface.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: December 6, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Wei Zheng, Keh-Chiang Ku, Howard E. Rhodes
  • Backside illuminated imaging sensor with vertical pixel sensor
    Patent number: 8063465
    Abstract: A backside illuminated imaging sensor includes a vertical stacked sensor that reduces cross talk by using different silicon layers to form photodiodes at separate levels within a stack (or separate stacks) to detect different colors. Blue light-, green light-, and red light-detection silicon layers are formed, with the blue light detection layer positioned closest to the backside of the sensor and the red light detection layer positioned farthest from the backside of the sensor. An anti-reflective coating (ARC) layer can be inserted in between the red and green light detection layers to reduce the optical cross talk captured by the red light detection layer. Amorphous polysilicon can be used to form the red light detection layer to boost the efficiency of detecting red light.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: November 22, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Howard E. Rhodes
  • IMAGE SENSOR WITH BACKSIDE PASSIVATION AND METAL LAYER
    Publication number: 20110278436
    Abstract: An image sensor includes a semiconductor layer that filters light of different wavelengths. For example, the semiconductor layer absorbs photons of shorter wavelengths and passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed near a front side of the semiconductor layer. A dopant layer is formed below the photodiode near a back side of the semiconductor layer. A mirror that primarily reflects photons of longer visible wavelengths is disposed on the back side of the semiconductor layer.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 17, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Howard E. Rhodes, Hidetoshi Nozaki
  • Semiconductor devices including damascene trenches with conductive structures
    Patent number: 8053899
    Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: November 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • LASER ANNEAL FOR IMAGE SENSORS
    Publication number: 20110260221
    Abstract: A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 27, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • SLEEVE INSULATORS AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20110254163
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT
    Publication number: 20110241090
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Buried conductor for imagers
    Patent number: 8018015
    Abstract: A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A first insulating layer is located over the photo-conversion device and the at least one contact area. The pixel cell further includes at least one conductor in contact with the at least one contact area. The conductor includes a polysilicon material extending through the first insulating layer and in contact with the at least one contact area. Further, a conductive material, which includes at least one of a silicide and a refractory metal, can be over and in contact with the polysilicon material.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 13, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Image sensor with backside passivation and metal layer
    Patent number: 8008695
    Abstract: An image sensor includes a semiconductor layer that low-pass filters light of different wavelengths. For example, the semiconductor layer proportionately absorbs photons of shorter wavelengths and proportionately passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed on a front surface of the semiconductor layer, where the photodiode is an N? region formed within the P-type region of the semiconductor layer. A P+ layer is formed between the N? region of the photodiode and a back surface of the semiconductor layer. A mirror that primarily reflects photons of red and/or infra-red wavelengths is formed on the back surface of the semiconductor layer.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: August 30, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Hidetoshi Nozaki
  • WAVEGUIDE FOR THERMO OPTIC DEVICE
    Publication number: 20110206332
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtel Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Single poly CMOS imager
    Patent number: 8003506
    Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 23, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Howard E. Rhodes
  • IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION
    Publication number: 20110199518
    Abstract: An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Wei Zheng, Hsin-Chih Tai, Yin Qian, Hongjun Li, Howard E. Rhodes
  • Image sensor having differing wavelength filters
    Patent number: 7990445
    Abstract: An image sensor includes filters formed over a portion of an array of photosensitive elements in a predetermined pattern. The pattern can be such that the exposure of a matrix (such as a 2-by-2 square of pixels) to light (such as blue light) is improved, while maintaining acceptable capability to capture light across the entire spectrum. The pattern can be such that two blue filters, one red, and one green filter is used by a 2-by-2 square matrix of pixels. The pattern can also include cyan, yellow, and magenta (CYM) filters.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 2, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Ian Montandon
  • Backside illuminated imaging sensor with silicide light reflecting layer
    Patent number: 7989859
    Abstract: A backside illuminated imaging sensor includes a semiconductor layer, a metal interconnect layer and a silicide light reflecting layer. The semiconductor layer has a front surface and a back surface. An imaging pixel that includes a photodiode region is formed within the semiconductor layer. The metal interconnect layer is electrically coupled to the photodiode region and the silicide light reflecting layer is coupled between the metal interconnect layer and the front surface of the semiconductor layer. In operation, the photodiode region receives light from the back surface of the semiconductor layer, where a portion of the received light propagates through the photodiode region to the silicide light reflecting layer. The silicide light reflecting layer is configured to reflect the portion of light received from the photodiode region.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: August 2, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Howard E. Rhodes
  • CMOS IMAGE SENSOR WITH SELF-ALIGNED PHOTODIODE IMPLANTS
    Publication number: 20110177650
    Abstract: An example method of forming a pinned photodiode includes applying a photoresist mask to a semiconductor layer at a location where a transfer gate will subsequently be formed. First dopant ions are then implanted at a first angle to form a first dopant region under an edge of the photoresist mask. Next, a photoresist mask is etched such that a thickness of the photoresist mask is reduced to form a trimmed photoresist mask. Second dopant ions are then implanted at a second angle to form a second dopant region, wherein the second dopant ions are shadowed by the trimmed photoresist mask to exclude the second dopant ions from a region partially above the first dopant region and adjacent to an edge of the trimmed photoresist mask.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 21, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Howard E. Rhodes
  • Frontside illuminated image sensor comprising a complex-shaped reflector
    Patent number: 7982177
    Abstract: An array of pixels is formed using a substrate, where each pixel has a substrate having an incident side for receiving incident light, a photosensitive region formed in the substrate, and a reflector having a complex-shaped surface. The reflector is formed in a portion of the substrate that is opposed to the incident side such that light incident on the complex-shaped surface of the reflector is reflected towards the photosensitive region.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 19, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hidetoshi Nozaki, Howard E. Rhodes
  • METHOD AND APPARATUS PROVIDING CMOS IMAGER DEVICE PIXEL WITH TRANSISTOR HAVING LOWER THRESHOLD VOLTAGE THAN OTHER IMAGER DEVICE TRANSISTORS
    Publication number: 20110169993
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Howard E. Rhodes
  • Method of fabricating a sleeve insulator for a contact structure
    Patent number: 7968403
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • PASSIVATION PLANARIZATION
    Publication number: 20110140222
    Abstract: A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on glass layer may be deposited over the non-uniform passivation layer prior to planarization. Once a uniform, flat first passivation layer is achieved over the final metal, a second passivation layer, a color filter array, or a lens forming layer with uniform thickness is formed over the first passivation layer. The passivation layers can be oxide, nitride, a combination of oxide and nitride, or other suitable materials. The color filter array layer may also undergo a planarization process prior to formation of the lens forming layer. The present invention is also applicable to other devices.
    Type: Application
    Filed: January 24, 2011
    Publication date: June 16, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Howard E. Rhodes
  • Image sensor and pixel that has positive transfer gate voltage during integration period
    Patent number: 7956913
    Abstract: A pixel and image sensor formed in accordance with the present invention has two modes of operation: a normal mode and a low light mode. The present invention switches from a normal to a low light mode based upon the amount of illumination on the image sensor. Once the level of illumination is determined, a decision is made by comparing the level of illumination to a threshold whether to operate in normal mode or low light mode. In low light mode, the reset transistor (for a 3T pixel) or the transfer transistor (for a 4T pixel) is biased positive.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: June 7, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventor: Howard E. Rhodes