Abstract: Disclosed is a wafer-scale chip structure including a semiconductor wafer and multiple dies on the semiconductor wafer. The dies can include at least two dies with different patterns of fill shapes. Also disclosed are wafer-scale chip design methods and systems. In the design methods and systems, post-chip layout wafer-level topography optimization is performed to, for example, minimize performance variations between dies of the same design within the wafer-scale chip. Specifically, across-wafer die placement and wafer-level topography information is used to custom design and/or select different patterns of fill shapes to be inserted into the layouts of dies placed at different locations across the wafer-scale chip (including different patterns to be inserted into the layouts of dies that have the same design) in order to generate a design that minimizes either all across-wafer thickness variations or at least across-wafer thickness variations associated with specific dies having the same specific design.

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Abstract: Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Abstract: Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

Abstract: A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis. One aspect of the invention includes a method including determining a direction of electrical current flow in a portion of a wiring layout; and placing at least one non-equiaxial hole shape within the portion of the wiring layout, wherein the non-equiaxial hole shape is arranged in the direction of electrical current flow. The invention accommodates the limitations of copper CMP within an automated tool without sacrificing the efficiency of a hand-tuned layout. The invention also includes a semiconductor device including at least one non-equiaxial hole shape.

Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Abstract: Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance of each contiguous metal fill structure. Capacitive coupling between the contiguous metal fill structures and the metal interconnect structures is minimized due to the fragmented structure of contiguous metal fill structures.

Abstract: Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.