Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: Improved, planarized semiconductor structures are described which are prepared by a method involving the creation of a series of subminimum (i.e., 50 to 500 angstroms thick) polysilicon pillars extending vertically upward from the base of a wide trench and depositing a conductor material by chemical vapor deposition over the pillars; the pillars prevent the formation of a depression within the trench when planarized.

Abstract: A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).

Abstract: Improved, planarized semiconductor structures are described. They are prepared by a method which involves the creation of a series of subminimum (i.e., 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.

Abstract: The invention provides a method for planarizing over a recessed area of a semiconductor structure. The method involves the creation of a series of subminimum (i.e. 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.

Abstract: Disclosed is an improved method of polishing a semiconductor wafer, which involves mounting the wafer to a wafer carrier comprising at least two materials having different coefficients of thermal expansion and regulating the temperature of the carrier, to thereby impart a convex (or concave) bias to the wafer. This provides an increased polishing action at the wafer center (or edges), so as to compensate for otherwise non-uniform radial polishing action across the wafer surface. Also disclosed, is an apparatus which incorporates the unique wafer carrier and temperature regulating means for achieving the desired degree of radial curvature of the wafer carrier.