Abstract: A mask system for use by a lithographic system to project an image of a circuit design. The design includes at least one large feature and at least one nearby small feature. The mask comprises one or more shapes on a mask to project an image of the nearby small feature and, on the same mask or on a different mask, an opaque shape to project an image of the large feature. The opaque shape includes in a field thereof at least one dummy clear shape of size and configuration insufficient to be resolved. Light from the lithographic projection system may be projected through the opaque shape and the dummy clear shape to resolve an image of the large circuit feature on a resist layer of a wafer without resolving the clear shape on the resist layer, while simultaneously increasing optical flare on the resolved large circuit feature image.

Abstract: A method and system of determining a localized measure of regional pattern density in a fabrication process of a chip are disclosed. In one embodiment, the method includes determining pattern density values for each cell of a plurality of cells of interest; averaging the pattern density values for each cell within a first selected region about a target cell to determine the localized measure of regional pattern density for the target cell; storing the localized measure of regional pattern density for the target cell; and repeating the averaging and the storing for each of the plurality of cells. The simplification of data allows for a localized measure of regional pattern density determination in much less time than conventional techniques.

Abstract: A method and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. The method and system comprises locating regions in a finished semiconductor design that do not contain as-designed shapes. The method and system generates dummy fill shapes in the regions at a predetermined final density and sizes the generated dummy shapes so that their local density is increased to a predetermined value. The method and system further creates corresponding trim shapes that act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density. The method and system can be implemented on a computer program product comprising a computer useable medium including a computer readable program.

Abstract: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.

Abstract: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

Abstract: Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures comprise diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures comprise active circuit structures.

Abstract: A method of generating dummy phase shapes in the layout of an alternating phase shift mask. The method comprises identifying a linewidth-sensitive feature and a large feature in the circuit design, and identifying a space therebetween. On the aItPSM mask layout there are provided opposing phase shifting shapes to project an image of the linewidth-sensitive feature and an adjacent dummy phase shifting shape corresponding in location to the space. The dummy phase shifting shape is disposed on the alternating phase shifting mask a distance sufficiently far from the at least two opposing phase shifting shapes, and from the corresponding location of the large feature in the design, such that light projected through the at least one dummy phase shifting shape by the lithographic system does not significantly affect the final projected images of the linewidth-sensitive feature and the large feature.

Abstract: Methods, systems, program products are disclosed that control placement of dummy shapes about sensitive circuit elements such that the dummy shapes are at least substantially similar for each circuit element even though the dummy shapes are auto-generated. In one embodiment, the invention includes providing dummy shape pattern pitch information to a designer, and allowing placement of circuit elements at integer multiples of one or more of the pitches such that the dummy shapes are at least substantially similar about each instance of the circuit element. Another embodiment includes allowing placement of a marker about a circuit element to indicate an area in which dummy shapes are to be substantially identical, and then using the marker to place the circuit element. Dummy shapes generated within the marker ensure substantially identical dummy shapes for each instance of the circuit element. The invention also includes the integrated circuits formed.

Abstract: Aligning metal fill shapes with corresponding holes of a metal shield is provided. The holes of the metal shield are laid out corresponding to a pre-selected grid referenced to a pre-selected origin. The metal fill shapes of the metal fill pattern, are arranged in accordance with the same pre-selected grid and referenced to the same pre-selected origin. Accordingly, regardless of the size or spacing of the metal fill holes, a metal fill shape will substantially align with a corresponding metal fill hole. Such alignment between metallization levels and the structure of the metal shield and metal fill shape pattern enhance the electric noise blocking properties of the metal shield in conjunction with the metal fill shape.

Abstract: A semiconductor structure and a process for fabricating the semiconductor structure. The structure includes a first and second rigid dielectric layer and a first non-rigid dielectric wiring level between such layers. The non-rigid layer includes at least one interconnect. Dummy fill shapes are associated with the non-rigid dielectric wiring level for preventing local stresses and deflections in the vicinity of the interconnect. In one aspect, the dummy fill shapes are in proximity to the interconnect which have a coefficient of thermal expansion substantially the same as the first and second rigid dielectric layer and/or provide that the average local CTE matches the CTE of the surrounding regions and the interconnect as a whole.

Abstract: An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.

Abstract: A semiconductor structure and a process for fabricating the semiconductor structure. The structure includes a first and second rigid dielectric layer and a first non-rigid dielectric wiring level between such layers. The non-rigid layer includes at least one interconnect. Dummy fill shapes are associated with the non-rigid dielectric wiring level for preventing local stresses and deflections in the vicinity of the interconnect. In one aspect, the dummy fill shapes are in proximity to the interconnect which have a coefficient of thermal expansion substantially the same as the first and second rigid dielectric layer and/or provide that the average local CTE matches the CTE of the surrounding regions and the interconnect as a whole.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.

Abstract: An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.

Abstract: A method for determining the AB etch endpoint during an silicon trench isolation fabrication process requires the introduction into the STI design a sufficient quantity of “dummy” diffusion structures that provide a strong endpoint signal during normal STI fabrication and, that which endpoint signal may be controlled by adjustment of the planarization shapes associated with the dummy diffusion structures.