Abstract: A manufacturing method of an oxide semiconductor thin film transistor according to the disclosure includes the following. A source and a drain are formed. A channel layer is formed between the source and the drain, wherein the channel layer is separated from the source and the drain. An insulation layer is formed, wherein the insulation layer covers the source, the drain, and the channel layer. A first conductor is at least formed in a first opening of the insulation layer, wherein the first conductor contacts the source and the channel layer. A second conductor is at least formed in a second opening of the insulation layer, wherein the second conductor contacts the drain and the channel layer.

Abstract: An oxide semiconductor thin film transistor includes a source, a drain, a channel layer, an insulation layer, a first conductor and a second conductor. The channel layer is disposed between the source and the drain, and separated from the source and the drain. The insulation layer covers the source, the drain and the channel layer. The first conductor is at least disposed in a first opening of the insulation layer so as to touch the source and the channel layer. The second conductor is at least disposed in a second opening of the insulation layer so as to touch the drain and the channel layer.

Abstract: An angle-adjustable lighting device includes a mounting device including a mounting base formed integral with or affixed to a pair of goggles, engineering cap, face shield or headphone and a plurality of arched retaining bars equiangularly spaced around the periphery of the mounting base and obliquely forwardly extending in direction toward each other, and a lighting device including a battery-operated LED, a switch operable to turn on/off the battery-operated LED and a rod member located at one lateral side thereof and terminating in a coupling ball that is detachably coupled to the arched retaining bars of the mounting device.

Abstract: The present provides a method for fabricating a thin film transistor including following steps. A substrate is provided. A gate is formed above the substrate. A first source is formed above the substrate. A channel is formed, in which one end of the channel contacts with the first source. A stop layer covering the one end of the channel and exposing another end of the channel is formed. A drain connected with the other end of the channel is formed. Moreover, the present invention also provides a thin film transistor fabricated by the method.

Abstract: The present provides a method for fabricating a thin film transistor including following steps. A substrate is provided. A gate is formed above the substrate. A first source is formed above the substrate. A channel is formed, in which one end of the channel contacts with the first source. A stop layer covering the one end of the channel and exposing another end of the channel is formed. A drain connected with the other end of the channel is formed. Moreover, the present invention also provides a thin film transistor fabricated by the method.

Abstract: An oxide semiconductor thin film transistor includes a source, a drain, a channel layer, an insulation layer, a first conductor and a second conductor. The channel layer is disposed between the source and the drain, and separated from the source and the drain. The insulation layer covers the source, the drain and the channel layer. The first conductor is at least disposed in a first opening of the insulation layer so as to touch the source and the channel layer. The second conductor is at least disposed in a second opening of the insulation layer so as to touch the drain and the channel layer.

Abstract: An oxide semiconductor thin film transistor (TFT) substrate includes a substrate, a source, a drain, a patterned transparent conductive layer, an oxide semiconductor layer, a gate and a gate dielectric layer. The source and drain are disposed on the substrate. The patterned transparent conductive layer includes a first transparent electrode, a second transparent electrode and a pixel electrode. The first and second transparent electrodes respectively cover an upper surface of the source and an upper surface of the drain. The pixel electrode connects to the drain. The oxide semiconductor layer contacts the first and second transparent electrodes. The gate dielectric layer is interposed between the oxide semiconductor layer and the gate.

Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.

Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.

Abstract: A mask is provided. The mask includes a plurality of first rows of openings and a plurality of second rows of openings. Each of the first rows of openings includes a plurality of first openings arranged in a row. The first openings located at different first opening rows are aligned in a column direction. Each of the second opening rows includes a plurality of second openings arranged in a row. The second openings located at different second rows of openings are aligned in the column direction. The first opening rows and the second opening rows are disposed alternately, and any one of the second rows of openings is located between two adjacent first rows of openings. The first openings and the second openings are alternately arranged in the row direction.

Abstract: A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion.

Abstract: A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion.

Abstract: A fabrication method of a minute pattern at least includes following steps. A first crystallizable material layer is formed on a base material. The first crystallizable material layer is patterned to form a plurality of first patterns on the base material. A distance between every two adjacent first patterns is greater than a width of each of the first patterns. A first treatment process is performed to crystallize the first patterns. A second crystallizable material layer is formed on the base material and covers the first patterns. The second crystallizable material layer is patterned to form a plurality of second patterns on the base material. Each of the second patterns is located between the first patterns adjacent thereto, respectively.

Abstract: A thin film transistor and a fabricating method thereof are provided. The thin film transistor includes a gate, a gate insulator, an oxide semiconductor layer, a source, a drain, and a light barrier. The gate insulator covers the gate. The oxide semiconductor layer is disposed on the gate insulator and located above the gate. The source and the drain are disposed on parts of the oxide semiconductor layer. The light barrier is located above the oxide semiconductor layer and includes a first insulator, an ultraviolet shielding layer, and a second insulator. The first insulator is disposed above the oxide semiconductor layer. The ultraviolet shielding layer is disposed on the first insulator. The second insulator is disposed on the ultraviolet shielding layer.

Abstract: A pixel array including first signal lines, second signal lines, switch devices, and pixel units coupling to the first signal lines and the second signal lines through the switch devices is provided. The first signal lines and the second signal lines are formed on different films. Each of the pixel units includes a common electrode line. In each of the pixel units of an ith row, the common electrode line has at least one first line segment and at least one second segment coupled to each other and formed on different films, and a distance between an (i?1)th first signal line and the first line segment is not equal to that between the (i?1)th first signal line and the second line segment. The first signal lines are either scan lines or data lines of the pixel array, and the second signal lines are the other kind.

Abstract: The resistance measuring device of the present invention includes switch transistors and switch conductive lines disposed between the bonding pads on a first substrate and between the bumps on a second substrate, such that the bonding pads and the bumps are conducted when the transistors are turned on, and the bonding resistance between at least one of the bonding pads and its corresponding bump can be directly measured.

Abstract: A pixel structure having capacitor compensation includes a thin-film transistor, and the thin-film transistor includes a source electrode, a drain electrode, a semiconductor layer and a gate electrode. The gate electrode includes a bar-shaped main part, and at least a protrusion part or two indention parts. One of the characteristics of the present invention lies in layout patterns of the drain electrode and gate electrode. An overlapping area between the drain electrode and gate electrode, and the position of the overlapping area can both be kept by virtue of the arrangement of the protrusion part or the indention parts of the gate electrode, even when the alignment between the drain electrode and gate electrode is changed. Therefore, the gate-drain capacitor (Cgd) will not be changed so that the quality of the liquid crystal display will be improved accordingly.

Abstract: A fabrication method of a minute pattern at least includes following steps. A first crystallizable material layer is formed on a base material. The first crystallizable material layer is patterned to form a plurality of first patterns on the base material. A distance between every two adjacent first patterns is greater than a width of each of the first patterns. A first treatment process is performed to crystallize the first patterns. A second crystallizable material layer is formed on the base material and covers the first patterns. The second crystallizable material layer is patterned to form a plurality of second patterns on the base material. Each of the second patterns is located between the first patterns adjacent thereto, respectively.

Abstract: A panel conductive film configuration system and method thereof are presented. A panel is configured with a plurality of groups of lines staggered in different groups, and ends of the lines are arranged in a staggered manner at two different lengths and include a film contact unit. A processing unit analyzes line widths of the groups of lines through images of the panel photographed by a photographing unit, and when configuring a film on the panel, a setting unit controls a configuration position of the film to adjust attachment areas between a plurality of line contact blocks of the film and each film contact unit.

Abstract: A transparent conductive layer and a first conductive layer are formed. A first photoresist layer having a first part and a second part with different thicknesses is as a mask to remove a portion of the first conductive layers to form a composite gate, and expose the transparent conductive layer of the pixel transmissive area and a portion of the transparent conductive layer in the pixel reflective area. The first photoresist layer is removed. A gate insulating layer and a semiconductor layer are formed. A second photoresist layer having a third part and a fourth part with different thicknesses is taken as a mask to remove a portion of the semiconductor layer and the gate insulating layer to form a contact opening and a channel layer. The second photoresist layer is removed. A patterned second conductive layer comprising a drain, a source and a reflective pattern is formed.