Abstract: A transparent conductive layer and a first conductive layer are formed. A first photoresist layer having a first part and a second part with different thicknesses is as a mask to remove a portion of the first conductive layers to form a composite gate, and expose the transparent conductive layer of the pixel transmissive area and a portion of the transparent conductive layer in the pixel reflective area. The first photoresist layer is removed. A gate insulating layer and a semiconductor layer are formed. A second photoresist layer having a third part and a fourth part with different thicknesses is taken as a mask to remove a portion of the semiconductor layer and the gate insulating layer to form a contact opening and a channel layer. The second photoresist layer is removed. A patterned second conductive layer comprising a drain, a source and a reflective pattern is formed.

Abstract: A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film transistor (TFT) is also provided. First, a substrate is provided. Then, a poly silicon island is formed on the substrate. After that, a gate insulating layer is formed to cover the poly silicon island. Then, a gate is formed on the gate insulating layer. After that, a source/drain is formed in the poly silicon island below one side and the other side of the gate respectively, and a channel layer is formed between the source/drain. At least one of the poly silicon island and the gate is formed according to the above mentioned method for forming the pattern.

Abstract: A fabricating method of display panel is provided. A first substrate having display area and non-display area is provided. A pixel array is formed in the display area of the first substrate, and at the same time, a spacer layer is formed in the non-display area. The spacer layer surrounds the display area. Next, a sealant is formed in the non-display area, and the spacer layer is disposed between the sealant and the pixel array. A second substrate is arranged above the first substrate, and the first substrate and the second substrate are fixed by using the sealant. The spacer layer can prevent the overflow sealant from contaminating the devices in the panel. The spacer layer is formed during the fabricating process of the pixel array, so that no extra fabrication cost is needed.

Abstract: A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film transistor (TFT) is also provided. First, a substrate is provided. Then, a poly silicon island is formed on the substrate. After that, a gate insulating layer is formed to cover the poly silicon island. Then, a gate is formed on the gate insulating layer. After that, a source/drain is formed in the poly silicon island below one side and the other side of the gate respectively, and a channel layer is formed between the source/drain. At least one of the poly silicon island and the gate is formed according to the above mentioned method for forming the pattern.

Abstract: A downward mechanism for support pins is applicable to a reactor of removable type. Support pins are located on the base of the reactor, and each support pin has a base thereunder. The downward mechanism has an elevator mechanism and a board fixed thereto. The board has several holes for the pin and the base to pass respectively therethrough. Each hole elongates into a slit allowing each of the support pins, only, to pass respectively therethrough.

Abstract: A method for fabricating a thin film transistor array substrate is provided. Wherein, a plurality of contact holes and recesses are formed in a protection layer disposed upon thin film transistors. Each recess comprises an under-cut profile while each contact hole exposes a drain-metal layer of a corresponding thin film transistor. Then, a transparent conductor layer is formed on the protection layer, which in turn fills in the contact holes so as to be electrically connected to the drain-metal layer. Besides, the transparent conductor layer automatically segregates at the recesses to form a plurality of pixel electrodes, whereby the plurality of pixel electrodes can be formed without the utilization of photolithography and etching processes and thus fabricating cost is lowered.

Abstract: A method of forming a thin film transistor is described. A polysilicon layer is formed over a substrate, wherein the polysilicon layer has a first region, a second region and a channel region between the first and second regions. A nitrogen doping process is carried out to dope nitrogen into the polysilicin layer. A gate insulating layer and a gate are sequentially formed over the polysilicon layer, wherein the gate is formed over the channel region. A doping process is performed so as to form a source and a drain in the first region and second region, respectively.

Abstract: An organic electroluminescent display and a method for fabricating the same are provided. The present invention provides an organic electroluminescent display panel, including: a substrate with a plurality of pixel regions, wherein a device region and a light-emitting region is defined in each pixel region; an active device array, disposed in the device regions of the substrate; a transparent electrode layer, disposed over the substrate and coupled to the active device array; a light-shielding layer, disposed over the substrate, wherein the light-shielding layer at least covers the active device array and exposes the transparent electrode layer in the light-emitting regions; an organic functional layer, disposed over the transparent electrode layer exposed by the light-shielding layer; and an upper electrode layer, disposed over the organic functional layer.

Abstract: A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

Abstract: A manufacturing method of a thin film transistor is provided. An amorphous silicon layer (a-Si layer) is formed on a substrate. A nitrogen-plasma is formed to form a silicon nitride layer on the a-Si layer, wherein the step of forming the silicone nitride layer and the step of forming the a-Si layer are in-situ. Next, the a-Si layer is transformed to a poly-silicon layer. The poly-silicon layer is patterned to form a poly-silicon island. Afterward a gate insulation layer is formed on the substrate covering the poly-silicon island. A gate is formed on the gate insulation layer above the poly-silicon island. A source/drain is formed in the poly-silicon island beside of the gate.

Abstract: A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

Abstract: A method of fabricating a lightly doped drain region of a low temperature polysilicon thin film transistor is provided. First, a polysilicon layer is formed over a substrate, and then a gate insulation layer is formed over the polysilicon layer. A gate buffer layer and a gate are formed over the gate insulation layer, wherein the gate is formed on the gate buffer layer and a portion of the gate buffer layer is exposed. Next, a doping process is performed to form the lightly doped drain region in the polysilicon layer underneath the exposed portion of the gate buffer layer. Thus, a low temperature polysilicon thin film transistor is formed via a simplified process and the overall fabrication cost can be reduced and the production efficiency can be substantially improved.

Abstract: A downward mechanism for support pins is applicable to a reactor of removable type. Support pins are located on the base of the reactor, and each support pin has a base thereunder. The downward mechanism has an elevator mechanism and a board fixed thereto. The board has several holes for the pin and the base to pass respectively therethrough. Each hole elongates into a slit allowing each of the support pins, only, to pass respectively therethrough.