Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a wiring layer having a metal line, and forming a patterned disposable material layer over the wiring layer and having an opening aligned with the metal line. The method also includes depositing a first dielectric film in the opening and in contact with the metal line, and removing the patterned disposable material layer to leave the first dielectric film. The method further includes depositing a second dielectric film over the first dielectric film, and etching the second dielectric film to form a trench above the first dielectric film. In addition, the method includes removing a portion of the first dielectric film to form a via hole under the trench, and depositing a conductive material in the trench and the via hole.

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a conductive line layer over a semiconductor substrate. The conductive line layer includes a metal line. The method also includes forming a conductive pillar on and in contact with the metal line. The method further includes depositing a dielectric layer over the conductive line layer to cover the conductive pillar, and etching the dielectric layer to form a trench. The conductive pillar is exposed through the trench. In addition, the method includes filling the trench with a conductive material to form a conductive line.

Abstract: A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.

Abstract: A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.

Abstract: A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.

Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MU) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.

Abstract: A method for forming a semiconductor device is provided. The method includes: providing a semiconductor substrate; forming a bottom electrode layer over the semiconductor substrate; forming a magnetic tunneling junction (MTJ) layer over the bottom electrode layer; forming a top electrode layer over the MTJ layer; and performing a single etch operation to etch the bottom electrode layer, the MTJ layer, and the top electrode layer, thereby forming a bottom electrode, a MTJ, and a top electrode respectively.

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.

Abstract: A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.

Abstract: Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.

Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.