Abstract: A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.

Abstract: A method for forming a semiconductor device is provided. The method includes: providing a semiconductor substrate; forming a bottom electrode layer over the semiconductor substrate; forming a magnetic tunneling junction (MTJ) layer over the bottom electrode layer; forming a top electrode layer over the MTJ layer; and performing a single etch operation to etch the bottom electrode layer, the MTJ layer, and the top electrode layer, thereby forming a bottom electrode, a MTJ, and a top electrode respectively.

Abstract: A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.

Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

Abstract: A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

Abstract: A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.

Abstract: A method includes depositing a first polymer layer over a first dielectric layer, forming a first opening and a second opening using an etching process, wherein the first opening and the second opening are partially through the first polymer layer, filling the first opening and the second opening with a conductive material to form a first metal line and a second metal line, applying a selective thermal curing process to the first polymer layer until portions of the first polymer layer surrounding the first metal line and the second metal line are cured, removing uncured portions of the first polymer layer through a cleaning process and depositing a second dielectric layer to form an air gap between the first metal line and the second metal line.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Abstract: A method includes depositing a first polymer layer over a first dielectric layer, forming a first opening and a second opening using an etching process, wherein the first opening and the second opening are partially through the first polymer layer, filling the first opening and the second opening with a conductive material to form a first metal line and a second metal line, applying a selective thermal curing process to the first polymer layer until portions of the first polymer layer surrounding the first metal line and the second metal line are cured, removing uncured portions of the first polymer layer through a cleaning process and depositing a second dielectric layer to form an air gap between the first metal line and the second metal line.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Abstract: A device includes a first conductive line in a first metallization layer over a dielectric layer, wherein the first conductive line is wrapped by a first polymer layer on three sides and the first conductive line and the dielectric layer are separated by a bottom portion of the first polymer layer, a second conductive line over the dielectric layer, wherein the second conductive line is wrapped by a second polymer layer on three sides and the second conductive line and the dielectric layer are separated by a bottom portion of the second polymer layer and an air gap between the first conductive line and the second conductive line.

Abstract: A device includes a first conductive line in a first metallization layer over a dielectric layer, wherein the first conductive line is wrapped by a first polymer layer on three sides and the first conductive line and the dielectric layer are separated by a bottom portion of the first polymer layer, a second conductive line over the dielectric layer, wherein the second conductive line is wrapped by a second polymer layer on three sides and the second conductive line and the dielectric layer are separated by a bottom portion of the second polymer layer and an air gap between the first conductive line and the second conductive line.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.